Freescale Semiconductor MPC5200B Chapter 21 Debug Support and JTAG Interface

Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 21-1
Chapter 21
Debug Support and JTAG Interface
21.1 Overview
The following sections are contained in this document:
•Section 21.2, TAP Link Module (TLM) and Slave TAP Implementation
•Section 21.3, TLM and TAP Signal Descriptions
•Section 21.4, Slave Test Reset (STRST)
•Section 21.5, TAP State Machines
•Section 21.6, e300 Core JTAG/COP Serial Interface
•Section 21.7, TLM Link DR Instructions
•Section 21.8, TLM Test Instructions, includes:
—Section 21.8.1, IDCODE
—Section 21.8.1.1, Device ID Register
•Section 21.9, e300 COP/BDM Interface
The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip
Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5200B's imbedded
Freescale MPC603e G2_LE processor. This interface provides a means for executing test routines and for performing software development
& debug functions.
21.2 TAP Link Module (TLM) and Slave TAP Implementation
The MPC5200B debug and development logic consists of:
• a master TAP Link Module (TLM), which implements the mandatory instructions of the IEEE JTAG 1149.1 standard.
• a slave JTAG TAP block dedicated to microprocessor debug functions, which are contained within the imbedded e300
microprocessor.
The master/slave TLM/TAP architecture is not yet an approved extension of the IEEE standard. It is, however, interface-compatible with the
standard.
The TLM state machine is active at all times.
The TLM and slave TAP blocks each consist of:
• a TAP Controller state machine
• Instruction Register (IR)
• instruction decode
• various Data Registers (DR)
There is no inherent limit to the number of slave TAP blocks. However, no more than one slave TAP Controller state machine, designated by
its asserted Enable, is active at any time. The slave TAP state machines have an Enable input and a Select output not present in the IEEE
standard.
• All slave Enable signals are generated by the TLM block. No more than one Enable signal is ever asserted at one time.
• All slave Select signals are inputs to the TLM block. Any number of Select signals may be asserted at any time.
The TLM block contains a Link DR that determines which, if any, slave TAP block is active.
• When a slave TAP block is inactive, its TAP Controller state machine is locked in the RunTestIdle state, preventing its IR and DRs
from shifting.
• When a slave TAP block is active, the TLM IR and DRs (except the TLM Link DR described below) are disabled. However, the
TLM state machine continues to respond to the TAP interface signals TRST, TCK, and TMS.
The TLM Link DR can be shifted while a slave TAP is active. This is done by loading the slave IR with an instruction that activates the Select
signal, then performing a DR scan operation. This only affects the TLM Link DR, because the TLM IR selected the Link DR to enable a slave
in the first place, and the TLM IR cannot change while a slave is active.