Initialization Sequence
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 14-37
Bits 31-27, 24-0—Reserved
14.9.4 Network Interface Options
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps Ethernet. The interface mode is
selected by the MII_MODE bit in the R_CNTRL register. In MII mode (R_CNTRL.MII_MODE = 1) there are 18 signals defined by the 802.3
standard and supported by the FEC. These are shown in Table14-1:
The 7-Wire serial interface (R_CNTRL.MII_MODE = 0) operates in what is generally referred to as the “AMD” mode.
The Ethernet transmitter is designed to work with almost no intervention from software. Once ETHER_EN is asserted and data appears in the
transmit FIFO the Ethernet MAC is able to transmit onto the network.
When the transmit FIFO fills to the watermark (defined by the X_WMRK register), the MAC transmit logic will assert TX_EN and start
transmitting the preamble sequence, the start frame delimiter, and then the frame information from the FIFO. However, the controller defers
the transmission if the network is busy (carrier sense is asserted). Before transmitting, the controller waits for carrier sense to become inactive,
then determines if carrier sense stays inactive for 60 bit times. If so, then the transmission begins after waiting an additional 36 bit times (96
bit times after carrier sense originally became inactive).
If a collision occurs during transmission of the frame (half-duplex mode), the Ethernet controller follows the specified backoff procedures and
attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so
that they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate
retransmission is necessary.
When all the frame data has been transmitted, the FCS (32-bit CRC) bytes are appended if the TC bit is set in the transmit frame control word.
If the ABC bit is set in the transmit frame control word, a bad CRC will be appended to the frame data regardless of the TC bit value. Following
the transmission of the CRC, the Ethernet controller writes the frame status information to the MIB block. Short frames are automatically
padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame buffer = 1).
The FEC frame interrupts may be generated as determined by the settings in the IMASK register.
Transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, XFIFO_UN and XFIFO_ERROR. If the transmit frame
length exceeds MAX_FL bytes the BABT interrupt will be asserted, however the entire frame will be transmitted (no truncation).
To pause transmission, set the GTS (Graceful Transmit Stop) bit in the X_CNTRL register. When the GTS is set the FEC transmitter stops
immediately if transmission is not in progress; otherwise, it continues transmission until the current frame either finishes or terminates with
a collision. After the transmitter has stopped the GRA (Graceful Stop Complete) interrupt is asserted. If GTS is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
14.9.5 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address recognition, CRC checking, short
frame checking and maximum frame length checking.
When the driver enables the FEC receiver by asserting ETHER_EN it will immediately start processing receive frames. When RX_DV asserts,
the receiver will first check for a valid PA/SFD header. If the PA/SFD is valid it will be stripped and the frame will be processed by the receiver.
If a valid PA/SFD is not found the frame will be ignored.
In 7-wire serial mode, the first 16 bit times of RX_D0 following assertion of RX_DV (RENA) are ignored. Following the first 16 bit times
the data sequence is checked for alternating 1s and 0s. If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the
frame is ignored. After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11
is detected, the PA/SFD sequence is complete.
Bits Name Description
0:4 — Reserved
5TC Transmit CRC, written by user
0 = End transmission immediately after the last data byte.
1 = Transmit the CRC sequence after the last data byte.
6 ABC Append Bad CRC, written by user
0 = No affect
1 = Transmit the CRC sequence inverted after the last data bye (regardless of TC value).
7:31 Reserved