Freescale Semiconductor MPC5200B Chapter 5 Clocks and Power Management

Overview
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 5-1
Chapter 5
Clocks and Power Management
5.1 Overview
The following sections are contained in this document:
•Clock Distribution Module (CDM)
•MPC5200B Clock Domains
•Power Management
•CDM Registers
5.2 Clock Distribution Module (CDM)
The CDM is the source of all internally generated clocks and reset signals. The MPC5200B clock generation uses two analog phase locked
loop (APLL) blocks. The system APLL takes an external reference frequency (nominal 27–33MHz) and generates the following internal
clocks. See Table 5 -1.
5.3 MPC5200B Clock Domains
The MPC5200B has 5 major clock domains, which are listed below. Details are given in the sections that follow.
•e300 Core Clock Domain—internal processor core frequency
•Processor Bus (XLB ) Clock Domain —internal e300 Core processor bus
•SDRAM Memory Controller Clock Domain
•IPB Clock Domain—programming register and peripheral interface frequency
•PCI Clock Domain
The following smaller peripheral clock domains can be asynchronous to the fundamental clock frequencies on MPC5200B:
Ethernet—The Ethernet Controller requires a 10MHz (10 Mbit operation) or 25MHz (100 Mbit operation) Tx/Rx clock. Both
clocks are inputs to the MPC5200B, supplied from the Ethernet physical device (ETH_RXCLK, ETH_TXCLK pins). The Ethernet
Controller Tx/Rx portion of the MPC5200B is asynchronous to the rest of MPC5200B.
USB—The Universal Serial Bus module Tx/Rx portion can be clocked by an external clock source (IR_USB_CLK pin) or by an
internally generated clock. Clock frequency must be 48MHz. When the clock source is externally supplied, the USB module Tx/Rx
portion is asynchronous to the rest of MPC5200B.
PSC—The PSC (Programmable Serial Controller) module is instantiated in the MPC5200B 6 times (PSC1 to PSC6). The PSC has
different modes of operation. In some cases the logic is clocked by internally generated clocks (i.e., UART mode), and in others the
PSC is clocked by external clock sources (i.e., CODEC mode). If the PSC logic is clocked from an external source then the logic is
asynchronous to the rest of the chip.
When the PSC6 is configured as IrDA—The Infrared Data Association module Tx/Rx portion can be clocked by an external clock
source (IR_USB_CLK pin) or by an internally generated clock.
— When generated internally, the clock source can be a fix 48MHz clock generator or a programmable clock generator (Mclk).
Table5-1. Clock Distribution Module
Clock Name Description
XLB CLOCK
(xlb_clk)
Microprocessor on-chip 64-bit XLB clock. This is the fundamental MPC5200B frequency.
MEM_CLOCK
(mem_clock)
SDRAM Controller memory clock supplied to external SDRAM devices. Max frequency is
132MHz. The memory clock frequency is always equal to the XLB frequency.
IPB CLock
(ipb_clk)
Intellectual Property Bus (IPB) clock.
PCI CLOCK
(pci_clk)
PCI Controller clock.
CORE CLOCK Clock for the e300 Core. The core APLL takes the XLB clock and generates the e300 clock.
48MHz CLOCK
USB CLOCK
48MHz clock for USB and IrDA (PSC6). This clock can be sourced internally from the CDM or from
an external source via the IrDA_USB_CLK pin.