MPC5200B Users Guide, Rev. 1
20-34 Freescale Semiconductor
Functional Description
20.8.5.1 BDLC Reception Control Bits
The only control bit which is used for message reception, the IMSG bit, is actually used to prevent message reception. When the IMSG bit is
set BDLC module interrupts of the CPU are inhibited until the next SOF symbol is received. This allows the BDLC module to ignore the
remainder of a message once the CPU has determined that it is of no interest. This helps reduce the amount of CPU overhead used to service
messages received from the SAE J1850 network, since otherwise the BDLC module would require attention from the CPU for each byte
broadcast on the network. The IMSG bit is cleared when the BDLC module receives an SOF symbol, or it can also be cleared by the CPU.
NOTE
While the IMSG bit can be used to prevent the CPU from having to service the BDLC module for
every byte transmitted on the SAE J1850 bus, the IMSG bit should never be used to ignore the
BDLC module’s own transmission. Because setting the IMSG bit prevents all BDLC State Vector
Register bits from being updated until an SOF is received, the user would not receive any further
transmit-related interrupts until another SOF was received, making it very difficult for the CPU to
complete the transmission correctly.
20.8.5.2 Receiving a Message with the BDLC module
Receiving a message using the BDLC module is extremely straight-forward. As each byte of a message is received and placed into the BDLC
Data Register, the BDLC module will indicate this to the CPU with an Rx Data Register Full (RDRF) status in the BDLC State Vector Register.
When an EOF symbol is received, indicating to the CPU that the message is complete, this too will be reflected in the BDLC State Vector
Register.
Outlined below are the basic steps to be followed for receiving a message from the SAE J1850 bus with the BDLC module. For an illustration
of this sequence, refer to Section Figure20-14., Basic BDLC Receive Flowchart.
• Step 1: When RDRF Interrupt Occurs, Retrieve Data Byte
When the first byte of a message following a valid SOF symbol is received that byte is placed in the BDLC Data Register, and an
RDRF state is reflected in the BDLC State Vector Register. No indication of the SOF reception is made, since the end of the previous
message is marked by an EOF indication. The first RDRF state following this EOF indication should allow the user to determine
when a new message begins.
The RDRF interrupt is cleared when the received byte is read from the BDLC Data Register. Once this is done, no further CPU
intervention is necessary until the next byte is received, and this step is repeated.
All bytes of the message, including the CRC byte, will be placed into the BDLC Data Register as they are received for the CPU to
retrieve.
• Step 2: When an EOF is Received, the Message is Complete
Once all bytes (including the CRC byte) have been received from the bus, the bus will be idle for a time period equal to an EOD
symbol. Once the EOD symbol is received, the BDLC module will verify that the CRC byte is correct. If the CRC byte is not correct,
this will be reflected in the BDLC State Vector Register.
If no In-Frame Response bytes are transmitted following the EOD symbol, the EOD will transition into an EOF symbol. When the
EOF is received it will be reflected in the BDLC State Vector Register, indicating to the user that the message is complete. If IFR
bytes do follow the first EOD symbol, once they are complete another EOD will be transmitted, followed by an EOF.
Once the EOF state is reflected in the BDLC State Vector Register, this indicates to the user that the message is complete, and that
when another byte is received it is the first byte of a new message.
20.8.5.3 Filtering Received Messages
No message filtering hardware is included on the BDLC module, so all message filtering functions must be performed in software. Because
the BDLC module handles each message on a byte-by-byte basis, message filtering can be done as each byte is received, rather than after the
entire message is complete. This enables the CPU to decide while a message is still in progress whether or not that message is of any interest.
At any point during a message, if the CPU determines that the message is of no interest the IMSG bit can be set. Setting the IMSG bit
commands the BDLC module not to update the BDLC State Vector Register until the next valid SOF is received. This prevents the CPU from
having to service the BDLC module for each byte of every message sent over the network.
20.8.5.4 Receiving Exceptions
As with a message transmission, this basic message reception flow can be interrupted if errors are detected by the BDLC module. This can
occur if an incorrect CRC is detected or if an invalid or out of range symbol appears on the SAE J1850 bus. A problem can also arise if the
CPU fails to service the BDLC Data Register in a timely manner during a message reception.
• Receiver Overrun