MPC5200B Users Guide, Rev. 1
20-38 Freescale Semiconductor
Functional Description
20.8.6.3 Transmit Single Byte IFR
The Transmit Single Byte IFR (TSIFR) bit in BDLC Control Register 2 is used to transmit Type 1 and Type 2 IFRs onto the SAE J1850 bus.
If this bit is set after a byte is loaded into the BDLC Data Register, the BDLC module will attempt to send that byte, preceded by the
appropriate Normalization Bit, as a single byte IFR without a CRC. If arbitration is lost, the BDLC module will automatically attempt to
transmit the byte again (without a Normalization Bit) as soon as the byte winning arbitration completes transmission. Attempts to transmit the
byte will continue until either the byte is successfully transmitted, the TEOD bit is set by the user or an error is detected on the bus.
The user must set the TSIFR bit before the EOD following the main part of the message frame is received, or no IFR transmit attempts will
be made for the current message. If another node does transmit an IFR to this message or a reception error occurs, the TSIFR bit will be
cleared. If not, the IFR will be transmitted after the EOD of the next received message.
The TSIFR bit will be automatically cleared once the EOD following one or more IFR bytes has been received or an error is detected on the
bus.
20.8.6.4 Transmit Multi-Byte IFR 1
The Transmit Multi-Byte IFR 1 (TMIFR1) bit is used to transmit an SAE J1850 Type 3 IFR with a CRC byte appended. If this bit is set after
the user has loaded the first byte of a multi-byte IFR into the BDLC Data Register, the BDLC module will begin transmitting that byte,
preceded by the appropriate Normalization Bit, onto the SAE J1850 bus. Once this happens a TDRE interrupt will occur, indicating to the user
that the next IFR byte should be loaded into the BDLC Data Register. When the last byte to be transmitted is written to the BDLC Data
Register, the user sets the TEOD bit. This will cause a CRC byte and an EOD symbol to be transmitted following the last IFR byte.
As with the TSIFR bit, the TMIFR1 bit must be set before the EOD symbol is received, or it will remain cleared and no IFR transmit attempt
will be made. The TMIFR1 bit will be cleared once the CRC byte and EOD are transmitted, if an error is detected on the bus, if a loss of
arbitration occurs during the IFR transmission or if a transmitter underrun occurs when the user fails to service the TDRE interrupt in a timely
manner. If a loss of arbitration occurs while the Type 3 IFR is being transmitted, transmission will halt immediately and the loss of arbitration
will be indicated in the BDLC State Vector Register.
20.8.6.5 Transmit Multi-Byte IFR 0
The Transmit Multi-Byte IFR 0 (TMIFR0) bit is used to transmit an SAE J1850 Type 3 IFR without a CRC byte appended. If this bit is set
after the user has loaded the first byte of a multi-byte IFR into the BDLC Data Register, the BDLC module will begin transmitting that byte,
preceded by the appropriate Normalization Bit, onto the SAE J1850 bus. Once this happens a TDRE interrupt will occur, indicating to the user
that the next IFR byte should be loaded into the BDLC Data Register. When the last byte to be transmitted is written to the BDLC Data
Register, the user sets the TEOD bit. This will cause an EOD symbol to be transmitted following the last IFR byte.
As with the TSIFR and TMIFR1 bits, the TMIFR0 bit must be set before the EOD symbol is received, or it will remain cleared and no IFR
transmit attempt will be made. The TMIFR0 bit will be cleared once the CRC byte and EOD are transmitted, if an error is detected on the bus,
if a loss of arbitration occurs during the IFR transmission or if a transmitter underrun occurs when the user fails to service the TDRE interrupt
in a timely manner. If a loss of arbitration occurs while the Type 3 IFR is being transmitted, transmission will halt immediately and the loss
of arbitration will be indicated in the BDLC State Vector Register.
NOTE
The TMIFR0 bit should not be used to transmit a Type 1 IFR. If a loss of arbitration occurs on the last
bit of a byte being transmitted using the TMIFR0 bit, two extra logic ones will be transmitted to
ensure that the IFR will not end on a byte boundary. This can cause an error in a Type 1 IFR.
20.8.6.6 Transmitting An IFR with the BDLC module
While the design of the BDLC module makes the transmission of each type of IFR similar, the steps necessary for sending each will be
discussed. Again, a discussion of the bytes making up any particular IFR is not within the scope of this document. For a more detailed
description of the use of IFRs on an SAE J1850 network, refer to the SAE J1850 document.

Table20-20. IFR Control Bit Priority Encoding

READ/WRITE ACTUAL
TSIFR TMIFR1 TMIFR0 TSIFR TMIFR1 TMIFR0
000000
1XX100
01X010
001001