Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-61
2. Set the PCI command, Max_Retries, and Max_Beats
3. Set mode, Continuous or Non-continuous
4. Reset the FIFO
5. Set the FIFO Alarm and Granularity fields
6. Set the Master Enable bit (eventually enable the wanted interrupt in case of errors or even of a normal termination)
7. Set the Reset Controller bit low
8. Setup the BestComm (eventually passing the parameters to the task if needed, enabling, if required, the Task to interrupt the Core
when finished, etc.)
9. Start the Task(s). It is not strictly necessary to start a PCI RX or TX task before starting the PCI to transmit/receive as one will
‘wait’ for the other to fill the data in or out of the FIFO.
10. Write the Packet Size value to fire off the transfer
10.4.6.5 Restart and Reset
A Restart sequence (namely writing of the Packet Size register) is required whenever the controller ends a packet transmission, either normally
or abnormally. In non-continuous mode, a new Start_Add address is generally required since this value is re-used as the start of the next packet
once it is Restarted. In Continuous mode, the Start_Add value is not reused. Instead, the next packet begins where the last one left off, but a
Restart sequence is still required to get this next packet started.
Writing a non-zero value to the Packet_Size register generates a Restart pulse to the controller. Depending on the desired mode of operation
other register accesses may be required, as described in the following paragraphs.
If Continuous mode is not selected, operation is fairly straight forward. Upon packet termination, Restart will not occur until Packet_Size is
written with a non-zero value, even if the packet size is the same it must be re-written. Master Enable bit was previously high and can remain
so. Reset Controller bit was previously low and can remain so. Toggling the Master Enable or Reset bit is unnecessary but would not disrupt
the transmit controller. If any other Control values, e.g. Start_Add, are to be changed they should be written either prior to writing the
Packet_Size value or written while the Master Enable bit is negated and the Reset Controller bit is negated. The recommended approach is to
write the control values in order (Packet_Size must be last) and not toggle the Master Enable bit. The Reset bit should remain negated.
If Continuous mode is active, basic operation is still straight forward. A Restart is achieved by writing the Packet_Size register to a non-zero
value (just as before). However, the Master Enable and Reset bits must not toggle in this case. If the Master Enable bit goes low the
Packets_Done counter will be reset. If the Reset bit goes high the Start_Add value will be re-loaded and subsequent transactions will begin at
this address. Therefore, the Master Enable bit can be used to reset the Packets_Done counter but without disturbing the current PCI address.
The Reset Controller bit will reset the counter and reload the Start_Add value into the transmit controller, thus achieving a total restart of a
continuous mode sequence. In any case, it is still required that the Packet_Size register be written to complete a Restart sequence.
The Master Enable bit, if negated, will prevent a Restart sequence but allows Control values to be updated without order dependency. A side
effect is to reset the Packets_Done counter and status, which is a concern in continuous mode only.
The Reset bit (RC bit of the RX/TX Enables register, NOT the external PCI RESET line), if asserted, will force a Reset of the controller. All
continuous mode effects will be reset and the Start_Add value is re-loaded. However, the Reset bit must be negated while the required write
to the Packet_Size register is accomplished. The Reset bit provides the only means to re-load the Start_Add value into the transmit controller
while Continuous mode is active. In either mode it provides a means to clear the transmit controller in cases of abnormal termination. Note,
a new Start_Add value must be written prior to setting the Reset bit.
10.4.6.6 PCI Commands
The expected PCI commands are Memory Write for transmit and Memory Read for receive. These are independent of cache or line size. This
permits the number of data beats per transaction to be flexible. If any requirements exist on number of data beats, then the software must
carefully consider the possibilities. If the Max_Beats setting does not divide properly into the Packet_Size setting then the packet will end up
with one or more single-beat transaction(s). Setting Max_Beats to 1 will force all transactions to be single-beat but will affect throughput.
In normal operation, all PCI byte enables will be asserted for PCI transactions through this interface, except if the 16-bit Word register bit is
set in the Section 10.3.3.1.3, Tx Transaction Control Register PCITTCR(RW) —MBAR + 0x3808 or Section 10.3.3.2.3, Rx Transaction
Control Register PCIRTCR(RW) —MBAR + 0x3888, in which case BE[3:0] = 1100.
Configuration writes to an external target should be handled exclusively by the XL bus Initiator interface.
10.4.6.7 FIFO Considerations
Careful consideration must also be given to filling and counting bytes of the Transmit FIFO and emptying and counting bytes of the Receive
FIFO. This operation is expected to be accomplished through Multi-Channel DMA which can also perform the register writes to the controller,
including necessary Restart sequences.