MPC5200B Users Guide, Rev. 1
A-4 Freescale Semiconductor
E
E
EA. . . . . . . . . . . . . . . . . . . . . Effective Address—The 32- or 64-bit address specified for a load, store, or instruction fetch. This address is
then submitted to the MMU for translation to either a physical memory address or an I/O address.
ED. . . . . . . . . . . . . . . . . . . . . Endpoint Descriptor
EEST. . . . . . . . . . . . . . . . . . . Enhanced Ethernet Serial Transceiver
en. . . . . . . . . . . . . . . . . . . . . . enable
EPROM. . . . . . . . . . . . . . . . . Erasable Programmable Read-Only Memory
err . . . . . . . . . . . . . . . . . . . . . error
ESAR . . . . . . . . . . . . . . . . . . Enhanced Segmentation And Reassembly
ETH. . . . . . . . . . . . . . . . . . . . Ethernet
Exception . . . . . . . . . . . . . . . A condition encountered by the processor that requires special, supervisor-level processing.
Exception handler. . . . . . . . . A software routine that executes when an exception is taken. Normally, the exception handler corrects the
condition that caused the exception, or performs some other meaningful task, which may include aborting the
program that caused the exception. The address for each exception handler is identified by an exception vector
offset defined by the architecture and a prefix selected by the MSR.
Extended opcode. . . . . . . . . . A secondary opcode field generally located in instruction bits 21–30, that further defines the instruction type.
All instructions are one word in length. The most significant 6 bits of the instruction are the primary opcode,
identifying the type of instruction. See also Primary opcode.
Execution synchronization. . . A mechanism by which all instructions in execution are architecturally complete before beginning execution
(appearing to begin execution) of the next instruction. Similar to context synchronization, but doesn't force
contents of the instruction buffers to be deleted and refetched.
Exponent. . . . . . . . . . . . . . . . In a floating-point number binary representation, the exponent is the component that signifies the integer power
to which the value two is raised in determining the value of the represented number. See also Biased exponent.
EXTAL . . . . . . . . . . . . . . . . . External Crystal. See also XTAL.
F
FBP. . . . . . . . . . . . . . . . . . . . Free Buffer Pool
FEC. . . . . . . . . . . . . . . . . . . . Fast Ethernet Controller
Fetch . . . . . . . . . . . . . . . . . . . Retrieving instructions from eith er the cache or main memory and placing them into the instruction queue.
FIFO . . . . . . . . . . . . . . . . . . . First-In-Fir st-Out (buffer)
FIR . . . . . . . . . . . . . . . . . . . . Fast Infrared. See also MIR and SIR.
FMC . . . . . . . . . . . . . . . . . . . Forward Monitor Cells
FPR. . . . . . . . . . . . . . . . . . . . Floating Point Register
FPSCR . . . . . . . . . . . . . . . . . Floating Point Status and Control Register
FPU. . . . . . . . . . . . . . . . . . . . Floating Point Unit
FRM . . . . . . . . . . . . . . . . . . . Forward Resource Management
flg . . . . . . . . . . . . . . . . . . . . . flag
FLT . . . . . . . . . . . . . . . . . . . . First-Level Table. See also SLT.
Fully-associative. . . . . . . . . . Addressing scheme where every cache location (every byte) can have any possible address.
G
Gb, Gbit . . . . . . . . . . . . . . . . Gigabit (written with lowercase b; 1024 megabits )
GB, GByte . . . . . . . . . . . . . . Giga-Byte (written with upper case B; 1024 MegaBytes )
GCI . . . . . . . . . . . . . . . . . . . . General Circuit Interface
GCRA. . . . . . . . . . . . . . . . . . Generic Cell Rate Algorithm ( leaky bucket)
GFC. . . . . . . . . . . . . . . . . . . . Generic Flow Control
GPCM. . . . . . . . . . . . . . . . . . General-Purpose Chip-select Machine
GPIO. . . . . . . . . . . . . . . . . . . General Purpose Input Output (standard)
GPR. . . . . . . . . . . . . . . . . . . . General-Purpose Register—Any of the 32 registers in the general-purpose register file. These registers provide
the source operands and destination results for all integer data manipulation instructions. Integer load
instructions move data from memory to GPRs and store instructions move data from GPRs to memory.
GPTMR. . . . . . . . . . . . . . . . . General Purpose Timer
GUI. . . . . . . . . . . . . . . . . . . . Graphical User Interface