Freescale Semiconductor MPC5200B - page 690

Memory Map and Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-11
After the byte in the BDLC Data Register has been loaded into the transmit shift register, the TDRE flag will be set in the BDLC State Vector
Register register, similar to the main message transmit sequence. If the interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt
request from the BDLC module is generated.The programmer should then load the next byte of the IFR into the BDLC Data Register for
transmission. When the last byte of the IFR has been loaded into the BDLC Data Register, the programmer should set the TEOD bit in the
BDLC control register 2. This will instruct the BDLC module to transmit a CRC byte once the byte in the BDLC Data Register is transmitted,
and then transmit an EOD symbol, indicating the end of the IFR portion of the message frame.
However, if the programmer wishes to transmit a single byte followed by a CRC byte, the programmer should load the byte into the BDLC
Data Register and then set the TMIFR1 bit before the EOD symbol has been received. Once the TDRE flag is set and interrupt occurs (if
enabled), the programmer should then set the TEOD bit in BDLC Control Register 2. This will result in the byte in the BDLC Data Register
being the only byte transmitted before the IFR CRC byte.
The user must set the TMIFR1 bit before the EOF following the main part of the message frame is received, or no IFR transmit attempts will
be made for the current message. If another node transmits an IFR to this message, the user must set the TMIFR1 bit before the normalization
bit is received or no IFR transmit attempts will be made for the message. If another node does transmit a successful IFR or a reception error
occurs, the TMIFR1 bit will be cleared. If not, the IFR will be transmitted after the EOD of the next received message.
If a transmitter underrun error occurs during transmission (caused by the programmer not writing another byte to the BDLC Data Register
following the TDRE flag being set) the BDLC module will automatically disable the transmitter after the byte currently in the shifter plus two
extra 1-bits have been transmitted. The receiver will pick this up as an framing error and relay it in the State Vector Regist er as an invalid
symbol error. The TMIFR1 bit will also be cleared.
If a loss of arbitration occurs when the BDLC module is transmitting a multiple byte IFR with CRC, the BDLC module will go to the loss of
arbitration state, set the appropriate flag and cease transmission. The TMIFR1 bit will be cleared and no attempt will be made to retransmit
the byte in the BDLC Data Register. If loss of arbitration occurs in the last bit of the IFR byte, two additional one bits (a passive long followed
by an active short) will be sent out.
NOTE
The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition
fault. This is helpful in preventing noise on the J1850 bus from corrupting a message.
TMIFR0 — Transmit Multiple Byte IFR with no CRC (Type 3)
This bit is used to request the BDLC module to transmit the byte in the BDLC Data Register as the first byte of a multiple byte IFR without
CRC. Response IFR bytes are still subject to J1850 message length maximums.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol has been received the BDLC
module will attempt to transmit the appropriate normalization bit followed by IFR bytes. The programmer should set TEOD after
the last IFR byte has been written into BDLC Data Register. After TEOD has been set, the last IFR byte to be transmitted will be
the last byte which was written into the BDLC Data Register.
0 = The TMIFR0 bit will be automatically cleared once the BDLC module has successfully transmitted the EOD symbol, by the
detection of an error on the multiplex bus, a transmitter underrun, or loss of arbitration.
After the byte in the BDLC Data Register has been loaded into the transmit shift register, the TDRE flag will be set in the BDLC State Vector
Register register, similar to the main message transmit sequence. If the interrupt enable bit (IE in BDLC Control Register 1) is set, an interrupt
request from the BDLC module is generated. The programmer should then load the next byte of the IFR into the BDLC Data Register for
transmission. When the last byte of the IFR has been loaded into the BDLC Data Register, the programmer should set the TEOD bit in the
BDLC Control Register 2. This will instruct the BDLC to transmit an EOD symbol, indicating the end of the IFR portion of the message frame.
The BDLC module will not append a CRC.
However, if the programmer wishes to transmit a single byte, the programmer should load the byte into the BDLC Data Register and then set
the TMIFR0 bit before the EOD symbol has been received. Once the TDRE flag is set and interrupt occurs (if enabled), the programmer should
then set the TEOD bit in BDLC Control Register 2. This will result in the byte in the BDLC Data Register being the only byte transmitted.
The user must set the TMIFR0 bit before the EOF following the main part of the message frame is received, or no IFR transmit attempts will
be made for the current message. If another node transmits an IFR to this message, the user must set the TMIFR0 bit before the normalization
bit is received or no IFR transmit attempts will be made for the message. If another node does transmit a successful IFR or a reception error
occurs, the TMIFR0 bit will be cleared. If not, the IFR will be transmitted after the EOD of the next received message.
If a transmitter underrun error occurs during transmission (caused by the programmer not writing another byte to the BDLC Data Register
following the TDRE flag being set) the BDLC module will automatically disable the transmitter after the byte currently in the shifter plus two
extra 1-bits have been transmitted. The receiver will pick this up as an framing error and relay it in the State Vector Regist er as an invalid
symbol error. The TMIFR0 bit will also be cleared.
If a loss of arbitration occurs when the BDLC module is transmitting a multiple byte IFR without CRC, the BDLC module will go to the loss
of arbitration state, set the appropriate flag and cease transmission. The TMIFR0 bit will be cleared and no attempt will be made to retransmit
the byte in the BDLC Data Register. If loss of arbitration occurs in the last bit of the IFR byte, two additional one bits (a passive long followed
by an active short) will be sent out.