MPC5200B Users Guide, Rev. 1
17-8 Freescale Semiconductor
Functional Description
17.4 Functional Description

17.4.1 General

The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are
dedicated to the SPI function as:
• Slave select (SS)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
While SPE is clear, SPI port pins 3, 2, 1, and 0 are general-purpose I/O (input/output) pins controlled by the SPI port data direction register.
The main element of the SPI system is the SPI data register. The 8-bit data register in the master and the 8-bit data register in the slave are
linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is
serially shifted eight bit positions by the SCK clock from the master; data is exchanged between the master and the slave. Data written to the
master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the
input data from the slave.
A write to the SPI data register puts data into a serial shifte. When a transfer is complete, received data is moved into a receive data register.
Data may be read from this double-buffered system any time before the next transfer is complete. This 8-bit data register acts as the SPI receive
data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data
buffer and for writing data to the shifter.
The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 select one of four possible clock
formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate
two fundamentally different protocols by shifting the clock by a half cycle or by not shifting the clock (17.4.4 Transmission Formats).
The SPI can be configured to operate as a master or as a slave. When MSTR in SPI control register 1 is set, the master mode is selected; when
the MSTR bit is clear, the slave mode is selected.

17.4.2 Master Mode

The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by
writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting
out on the MOSI pin under the control of the serial clock.
The SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI
baud rate register control the baud rate generator and determine the speed of the shift register. The SCK pin is the SPI clock output. Through
the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and MSTR
control bits.
Bit Name Description
0:7 DDR[0 :7] In SPI slave mode, SPIDDR bit 3 has no meaning or effect.
In SPI master mode, SPIDDR bit 3 determines if SPI port pin 3 is:
• an error-detect input to SPI
• a general-purpose output
• a slave select output line
Note: When SPI is Enabled, MISO, MOSI, and SCK are:
• inputs if expected to be inputs, regardless of associated data direction bit state.
• outputs if expected to be outputs, only if associated data direction bit is set.
SPIDDR bits 0:7—SPI Port Data Direction Control bits
0 = Associated pin is an input
1 = Associated pin is an output