Freescale Semiconductor MPC5200B - page 521

MPC5200B Users Guide, Rev. 1
15-10 Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
3 ORERR Overrun Error
Indicates whether an overrun occurs. For purposes of overrun, FIFO full means all FIFO space
is occupied; the Rx FIFO threshold is irrelevant to overrun.
0 = No overrun occurred.
1 = One or more characters in Rx data stream were lost. ORERR sets on receipt of a new
character when FIFO is full and a character is already in the shift register waiting for an empty
FIFO position. When this occurs, the character in the Rx shift register and its break detect,
framing error status, and parity error, if any, are lost. ORERR is cleared by the RESET ERROR
STATUS command in CR.
Also see the note on the end of this table.
4 TxEMP/
URERR
UART / SIR—Transmitter Empty
0 = Tx buffer not completely empty. Either a character is being shifted out, or Tx is disabled.
Tx is enabled/disabled by programming CR [TC].
1 = Tx has underrun (both the Tx holding register and Tx shift registers are empty). This bit
sets after transmission of the last stop bit of a character, if there are no characters in the Tx
holding register awaiting transmission.
other Modes—Underrun error
0 = No error.
1 = Underrun error occurred, which means the number of Tx FIFO bytes is 0, the Tx shift
register is empty, and a FrameSync occurs. In other words, the time has come to transmit a
new sample, but no sample is available in the Tx shift register. Unlike UART mode, TxEMP
high indicates an error condition similar to the overrun condition (ORERR = 1), and as such
it is now cleared the same way as ORERR, by a RESET ERROR STATUS command in the
CR and not by a reset Tx command in the CR.
Also see the note on the end of this table.
5 TxRDY Transmitter Ready
0 - Tx FIFO contains a number of data bytes greater than the TFALARM register value, or the
Tx is disabled.
1 - Tx FIFO is “almost empty” as defined by the TFALARM. TxRDY sets when the number of
Tx FIFO bytes falls to, or below, the TFALARM value, due to data transfer from the Tx FIFO
to the Tx shift register. Once set, TxRDY remains set until the number of empty bytes in the
Tx FIFO falls to 4 times the granularity level specified in the TFCNTL register. In UART mode
this bit only asserts if the Tx is enabled.
Also see the note on the end of this table.
6 FFULL Rx FIFO full
0 = The Rx FIFO is not “almost full”
1 = Rx FIFO is “almost full” as defined by the RFALARM. FFULL sets as soon as the number
of bytes in the Rx FIFO exceeds the RFALARM value, due to the transfer of data from the Rx
shift register to the Rx FIFO. Once set, FFULL remains set until the number of bytes in the
Rx FIFO falls to the granularity level specified in the RFCNTL register.
Also see the note on the end of this table.
7 RxRDY Receiver Ready
0 = There is no data in the Rx FIFO.
1 = One or more characters were received and are waiting in the Rx buffer FIFO.
Also see the note on the end of this table.
Bit Name Description