Freescale Semiconductor MPC5200B 8.6 Programming the SDRAM Controller, 8.7 Memory Controller Registers (MBAR+0x0100:0x010C)

MPC5200B Users Guide, Rev. 1

8-20 Freescale Semiconductor

Programming the SDRAM Controller

If all the memory and controller register values have been precalculated and stored in ROM, skip step 3 and go directly to step 4.

Otherwise, continue with step 3.

Step 3. Read the SDRAM parameters (type, size, address muxing, timing), and determine the memory clock frequency. (The memory

clock frequency is always equal to the XLB frequency.) Using the SDRAM parameters and the clock frequency, calculate all the

memory and controller register values now. Certain register fields are mandatory:

— Memory Mode register Burst Mode = Sequential

— Memory Mode register Burst Length = 8

— Controller Configuration register 2 burst_length = 7

— Controller Control register cke = 1

Do not write any registers yet. Use these register values as default values for the following operations. An operation can override

the default, but overrides do not carry forward to subsequent operations.

Step 4. Write the SDRAMCS Configuration registers and the controller Config registers 1 & 2.

Step 5. Write the controller Control register with these overrides:

— assert the mode_en bit (1).

— negate ref_en (0).

Step 6. (DDR only) Write the controller Control register to issue a Precharge All Banks command (soft_pre=1); maintain mode_en=1,

ref_en=0, all other bits default.

Step 7. (DDR only) Write to the memory Extended Mode register to enable the DLL.

Step 8. (DDR only) Write to the memory Mode register to reset the DLL.

Step 9. (DDR only) Pause for the DLL lock time specified by the memory (roughly 100 µs. See memory datasheet for detailed time).

Step 10.Write to the controller Control register to issue a Precharge All Banks command (soft_pre=1); maintain mode_en=1, ref_en=0.

Step 11.Write to the controller Control register to issue 2 or more Auto Refresh commands (soft_ref=1); maintain mode_en=1, ref_en=0.

Each command requires a separate write.

Step 12.Write to the memory Mode register to specify normal operation.

Step 13.Write to the controller Control register to specify normal operation.

The MPC5200B implements a self-calibrating, software adjustable, read clock recovery circuit. A 400 tap master delay chain, continuously

measures either the half or full period delay of the memory clock. The master tap value is used to derive a 1/4 period tap value, for use in 4

independent, 256 tap, slave delay chains. In DDR mode, the MDQS signal is used to generate the 1/4 period delayed read clock. In SDR mode,

an internally generated “DQS” signal is used to generate the 1/4 period delayed read clock. For both DDR and SDR memories, the delayed

read clock is used to latch the data from the memories.

8.6 Programming the SDRAM Controller

The Memory Controller registers consist of:

•Section Table8-5., Memory Controller Mode Register / SDRAM MC Extended Mode Register (MBAR+0x0100), write only

•Section Table8-6., Memory Controller Control Register (MBAR+0x0104)

•Section Table8-10., Memory Controller Configuration Register 1 (MBAR+0x0108)

•Section Table8-11., Memory Controller Configuration Register 2 (MBAR+0x010C)

All registers are 32bit-aligned in memory (modulo 4 address boundary).

8.7 Memory Controller Registers (MBAR+0x0100:0x010C)

Each time the 32-bit write-only Mode register (mode[0:31]) is written (and cmd is set to 1), the controller generates a Load Mode Register or

Load Extended Mode Register command to memory.

The memory Mode/Extended Mode registers must be initialized during the system boot sequence; but before writing to the controller Mode

register, the mode_en and cke bits in the Control register must be set to 1. After memory initialization is complete, the Control register

mode_en bit should be cleared to prevent subsequent access to the controller Mode register.