Freescale Semiconductor MPC5200B 10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) MBAR + 0x38C0, 10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) MBAR + 0x38C4

Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-41
10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) —MBAR + 0x38C0
10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) —MBAR + 0x38C4
12 System Error
(SE)
This flag is set in response to the Transmit Controller entering an illegal state. A CPU
interrupt will be generated if the System error Enable (SE) bit is set. In normal operation this
should never occur. The only recovery is to assert the Reset Controller bit, PCIRER[RC],
and clear this flag.
13 Retry Error
(RE)
This flag is set if Max_Retries is set to a finite value (0x01 to 0xff) and the PCI transaction
has performed retries in excess of the setting. A CPU interrupt will be generated if the Retry
error Enable (RE) bit is set. The retry counter is reset at the beginning of each transaction
(i.e. it is not cumulative throughout a packet) and would generally indicate a broken or
improperly accessed Target.
14 Target Abort
(TA)
This flag bit is set if the PCI controller has issued a Target Abort (which means the
addressed PCI Target has signalled an Abort). A CPU interrupt will be generated if the
Target Abort Enable (TAE) bit is set. It is up to application software to query the Target’s
status register and determine the source of the error. The coherency of the Receive FIFO
data and the Receive Controller’s status registers (Next_Address, Bytes_Done, etc.) should
remain valid.
15 Initiator Abort
(IA)
This flag bit is set if the PCI controller issues an Initiator Abort flag. This indicates that no
Target responded but further status information can be read from the PCI Configuration
interface. A CPU interrupt will be generated if the Initiator Abort error Enable (IAE) bit is
set. The coherency of the Receive FIFO data and the Receive Controller’s status registers
(Next_Address, Bytes_Done, etc.) should remain valid.
16:31 Reserved Unused. Software should write zero to these bits.
msb 012345678 9 101112131415
R FIFO_Data_Word
W
RESET uninitailized random 16 bit value
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R FIFO_Data_Word
W
RESET uninitalized random 16 bit value
Bits Name Description
0:31 FIFO_Data_Word FIFO data port—Reading from this location “pops” data from the FIFO; writing “pushes”
data into the FIFO. During normal operation the Multi-Channel DMA controller pops
data here. The receive controller pushes data. Therefore, user programs should not
write here. At power on reset an uninitialized random value is read at this register. A
FIFO reset must be always performed before first accessing the FIFO.
Note: Only full 32-bit accesses are allowed. If all Byte enables are not asserted when
accessing this location, FIFO data will be corrupted.
msb 012345678 9 101112131415
RESET 0 00000000 0 0 000 0 1
Bits Name Description