MPC5200B Users Guide, Rev. 1
A-10 Freescale Semiconductor
S
Scalability. . . . . . . . . . . . . . . The capability of an architecture to generate implementations specific for a wide range of purposes, and in
particular implementations of significantly greater performance and/or functionality than at present, while
maintaining compatibility with current implementations.
Scan chain. . . . . . . . . . . . . . . The peripheral buffers of a device, linked in JTAG test mode, that are addressed in a shift-register fashion.
SCC. . . . . . . . . . . . . . . . . . . . Serial Communication Controller
SCP. . . . . . . . . . . . . . . . . . . . Serial Control Port
SCR. . . . . . . . . . . . . . . . . . . . Sustained Cell Rate
SDLC . . . . . . . . . . . . . . . . . . Synchronous Data Link Control
SDRAM . . . . . . . . . . . . . . . . Synchronous Dynamic RAM—a faster version of DRAM. SDRAM is generally synchronized with the clock
speed for which the microprocessor is optimized. This tends to increase the number of instructions the processor
can perform in a given time. The speed of SDRAM is rated in MHz rather than in nanoseconds (ns). This makes
it easier to compare the bus speed and the RAM chip speed. You can convert the RAM clock speed to
nanoseconds by dividing the chip speed into 1 billion ns (which is one second). For example, an 83MHz RAM
would be equivalent to 12ns.
sel . . . . . . . . . . . . . . . . . . . . . select
Set (v) . . . . . . . . . . . . . . . . . . To write a non-zero value to a bit or bit field; the opposite of clear. The term "set" may also be used to generally
describe the updating of a bit or bit field.
Set (n) . . . . . . . . . . . . . . . . . . A subdivision of a cache. Cacheable data can be stored in a given location in any one of the sets, typically
corresponding to its lower-order address bits. Because several memory locations can map to the same location,
cached data is typically placed in the set whose cache block corresponding to that address was least recently
used (LRU). See also Set-associative.
Set-associative . . . . . . . . . . . Aspect of cache organization in which cache space is divided into sections, called sets. The cache controller
associates a particular main memory address with the contents of a particular set, or region, within the cache.
Signals. . . . . . . . . . . . . . . . . . See Section X XX
Significand . . . . . . . . . . . . . . The component of a binary floating-point number that consists of an explicit or implicit leading bit to the left
of its implied binary point and a fraction field to the right.
SI. . . . . . . . . . . . . . . . . . . . . . Serial Interface
SIM. . . . . . . . . . . . . . . . . . . . System Integration Module
SIMM . . . . . . . . . . . . . . . . . . Signed IMMediate Value, or Single In-line Memory Module
SIP. . . . . . . . . . . . . . . . . . . . . Serial Infrared Interaction Pulse
SIR . . . . . . . . . . . . . . . . . . . . Slow Infrared. See also FIR and MIR.
SIU . . . . . . . . . . . . . . . . . . . . Systems Interface Unit
Slave . . . . . . . . . . . . . . . . . . . A device that responds to the m aster’s address. A slave receives data on a write cycle and gives data to the
master on a read cycle.
SLT . . . . . . . . . . . . . . . . . . . . Second-Level Tables. See also FLT.
SLTMR. . . . . . . . . . . . . . . . . Slice Timer
SMC . . . . . . . . . . . . . . . . . . . Serial Management Controllers
SNA . . . . . . . . . . . . . . . . . . . Systems Network Architecture
SPI. . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface—the SPI channel supports the out-of-band control channel to external physical
chips. The SPI module allows full-duplex, synchronous, serial communication between the MPC5200B and
peripheral devices. It supports master and slave mode, double-buffered operation and can operate in a polling
or interrupt driven environment.
SPR. . . . . . . . . . . . . . . . . . . . Special-Purpose Register
SR . . . . . . . . . . . . . . . . . . . . . Segment Register
SRAM. . . . . . . . . . . . . . . . . . Static Random Access Memory—a type of memory that is faster and more reliable than the more common
DRAM (Dynamic RAM). The term "static" is derived from the fact that it does not need to be refreshed like
DRAM.
SRR0. . . . . . . . . . . . . . . . . . . machine Status save/Restore Register 0
SRR1. . . . . . . . . . . . . . . . . . . machine Status save/Restore Register 1
SRTS. . . . . . . . . . . . . . . . . . . Synchronous Residual Time Stamp
SRU. . . . . . . . . . . . . . . . . . . . System Register Uni t
sta . . . . . . . . . . . . . . . . . . . . . status
Static branch prediction . . . . Mechanism by which software (for example, compilers ) can give a hint to the machine h ardware about the
direction a branch is likely to take.
STB. . . . . . . . . . . . . . . . . . . . Set-Top Box
Sticky bit. . . . . . . . . . . . . . . . A bit that when set must be cleared explicitly.