MPC5200B Users Guide, Rev. 1
14-44 Freescale Semiconductor
Initialization Sequence
If a collision occurs within 64 byte times the retry process is initiated. The transmitter waits a random number of slot times. A slot time is 512
bit times. If a collision occurs after 64 byte times no retransmission is performed and the end of frame buffer is closed with an LC error
indication.
14.9.10 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode both of the FIFOs are used and the FEC
actually operates in a full-duplex fashion. Both internal and external loopback are configured using combinations of the LOOP and DRT bits
in the R_CNTRL register and the FDEN bit in the X_CNTRL register.
For both internal and external loopback set FDEN = 1.
For internal loopback set LOOP = 1 and DRT = 0. TX_EN and TX_ER will not assert during internal loopback. During internal loopback the
transmit/receive data rate is higher than in normal operation because the internal system clock is used by the transmit and receive blocks
instead of the clocks from the external transceiver. This will cause an increase in the required system bus bandwidth for transmit and receive
data being transferred to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames
to prevent transmit FIFO underrun and receive FIFO overflow.
For external loopback set LOOP = 0, DRT = 0 and configure the external transceiver for loopback.
14.9.11 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the FEC BDs (receive), the IEVENT register and the
MIB block counters.

14.9.11.1 Transmission Errors

Transmitter Underrun
— If this error occurs the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame
are then flushed and closed. The UN bit is set in the X_STATUS register. The FEC will then continue to the next transmit buffer
descriptor and begin transmitting the next frame.
— The XFIFO_UN interrupt will be asserted if enabled in the IMASK register.
Carrier Sense Lost During Frame Transmission
— When this error occurs and no collision is detected in the frame the FEC sets the CSL bit in X_STATUS register. The frame is
transmitted normally. No retries are performed as a result of this error.
— No interrupt is generated as a result of this error.
Retransmission Attempts Limit Expired
— When this error occurs the FEC terminates transmission. All remaining buffers for that frame are then flushed and closed and
the RL bit is set in the X_STATUS register. The FEC will then continue to the next transmit buffer descriptor and begin
transmitting the next frame.
— The COL_RETRY_LIM interrupt will be asserted if enabled in the IMASK register.
Late Collision
— When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates transmission. All remaining
buffers for that frame are then flushed and closed and the LC bit is set in the X_STATUS register. The FEC will then continue
to the next transmit buffer descriptor and begin transmitting the next frame.
— The LATE_COL interrupt will be asserted if enabled in the IMASK register.
Heartbeat
— Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a good self-test the transceiver
indicates a collision to the FEC within 20 clocks after completion of a frame transmitted by the Ethernet controller. This
indication of a collision does not imply a real collision error on the network but is rather an indication that the transceiver still
seems to be functioning properly. This is called the heartbeat condition.
— If the HBC bit is set in the X_CNTRL register and the heartbeat condition is not detected by the FEC after a frame transmission
a heartbeat error occurs. When this error occurs the FEC closes the buffer, sets the HB bit in the X_STATUS register and
generates the HBERR interrupt if it is enabled.

14.9.11.2 Reception Errors

Overrun Error
— If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the receive
status word. All subsequent data in the frame will be discarded and subsequent frames may also be discarded until the receive
FIFO is serviced by the DMA and space is made available. At this point the receive frame/status word is written into the FIFO
with the OV bit isset. This frame must be discarded by the driver.