MPC5200B Users Guide, Rev. 1
14-38 Freescale Semiconductor
Initialization Sequence
In MII mode the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected
prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected the frame, the receive FIFO is
signalled that the frame is “accepted” and may be passed on to the DMA. If the frame is a runt (due to collision) or is rejected by address
recognition, the receive FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions,
which indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire frame is written into the FIFO, a 32-bit frame
status word is written into the FIFO. This status word contains the M, BC, MC, LG, NO, SH, CR, OV and TR status bits, and the frame length.
The Ethernet controller receives serial data LSB first.
14.9.6 Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual (unicast), group (multicast) or broadcast (all-ones
group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field.
A flowchart for address recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. The flowchart shown
in Figure14-4 illustrates the address recognition decisions made by the receive block, while Figure 14-5 illustrates the decisions made by the
microcontroller.
If the DA is a broadcast address and broadcast reject (R_CNTRL.BC_REJ) is deasserted, then the frame will be accepted unconditionally as
shown in Figure 14-4. Otherwise, if the DA in not a broadcast address the microcontroller runs the address recognition subroutine as shown
in Figure 14-5.
If the DA is a group (multicast) address and flow control is disabled the microcontroller will perform a group hash table lookup using the
64-entry hash table programmed in GADDR1 and GADDR2. If a hash match occurs AR_HM_B (address recognition hash match bar) is set
to 0 and the receiver accepts the frame. If flow control is enabled the microcontroller will do an exact address match check between the DA
and the designated PAUSE DA in registers XMIT.FDXFC_DA1 and XMIT. FDXFC_DA2. In the case where a PAUSE DA exact match occurs
AR_EM_B (address recognition exact match bar) is set to 0. If the receive block determines that the received frame is a valid PAUSE frame
the frame will be rejected. Note the receiver will detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast
physical address.
If the DA is the individual (unicast) address the microcontroller performs an individual exact match comparison between the DA and 48-bit
physical address that the user programs in the PADDR1 and PADDR2 registers. If an exact match occurs AR_EM_B is set to 0; otherwise,
the microcontroller does an individual hash table lookup using the 64-entry hash table programmed in registers IADDR1 and IADDR2. In the
case of an individual hash match AR_HM_B is set to 0. Again, the receiver will accept or reject the frame based on PAUSE frame detection,
shown in Figure 14-4.
If neither a hash match (group or individual) nor an exact match (group or individual) occur both AR_HM_B and AR_EM_B are set to 1. In
this case, if promiscuous mode is enabled (R_CNTRL.PROM = 1), then the frame will be accepted and the MISS bit in the receive buffer
descriptor is set; otherwise, the frame will be rejected and the MISS bit will be cleared.
Similarly, if the DA is a broadcast address, broadcast reject (R_CNTRL.BC_REJ) is asserted and promiscuous mode is enabled. Then the
frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected and the MISS bit will be
cleared.
In general, when a frame is rejected it is flushed from the FIFO.