Modes of Operation
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 20-3
•Run
This mode is entered from the BDLC Disabled mode when the BDLCE bit in the BDLC Control Register is set. It is entered from
the BDLC Wait mode whenever activity is sensed on the J1850 bus or some other MCU source wakes the CPU out of Wait mode.
It is entered from the BDLC Stop mode whenever network activity is sensed or some other MCU source wakes the CPU out of Stop
mode. Messages will not be received properly until the clocks have stabilized and the CPU is also in the Run mode.
•BDLC Wait
This power conserving mode is automatically entered from the Run mode whenever the CPU executes a WAIT instruction and if
the WCM bit in the BDLC Control Register 1 register is previously cleared. In this mode, the BDLC module internal clocks continue
to run. Any activity on the J1850 network will cause the BDLC module to exit BDLC Wait mode and generate an unmaskable
interrupt of the CPU. This wakeup interrupt state is reflected in the BDLC State Vector Register, encoded as the highest priority
interrupt. This interrupt can be cleared by the CPU with a read of the BDLC State Vector Register.
– Wakeup from BDLC Wait with CPU in WAIT
If the CPU executes the WAIT instruction and the BDLC module enters the WAIT mode (WCM = 0), the clocks to the BDLC
module as well as the clocks in the MCU continue to run. Therefore, the message which wakes up the BDLC module from WAIT
and the CPU from WAIT mode will also be received correctly by the BDLC module. This is because all of the required clocks
continue to run in the BDLC module in WAIT mode.The wakeup behavior of the BDLC module applies regardless of whether the
BDLC module is in normal or 4X mode when the WAIT instruction is executed.
•BDLC Stop
This power conserving mode is automatically entered from the Run mode whenever the CPU executes a STOP instruction, or if the
CPU executes a WAIT instruction and the WCM bit in the BDLC Control Register 1 register is previously set. In this mode, the
BDLC internal clocks are stopped. Any activity on the network will cause the BDLC module to exit BDLC Stop mode and generate
an unmaskable interrupt of the CPU. This wakeup interrupt state is reflected in the BDLC State Vector Register, encoded as the
highest priority interrupt. This interrupt can be cleared by the CPU with a read of the BDLC State Vector Register. Depending upon
which low-power mode instruction the CPU executes to cause the BDLC module to enter BDLC Stop, the message which wakes
up the BDLC module (and the CPU) may or may not be received. There are two different possibilities, both of which is described
below. These descriptions apply regardless of whether the BDLC module is in normal or 4X mode when the STOP or WAIT
instruction is executed.
– Wakeup from BDLC Stop with CPU in STOP
When the CPU executes the STOP instruction, all clocks in the MCU, including clocks to the BDLC module, are turned off.
Therefore, the message which wakes up the BDLC module and the CPU from STOP mode will not be received. This is due primarily
to the amount of time required for the MCU’s oscillator to stabilize before the clocks can be applied internally to the other MCU
modules, including the BDLC module.
– Wakeup from BDLC Stop with CPU in WAIT
If the CPU executes the WAIT instruction and the BDLC module enters the Stop mode (WCM = 1), the clocks to the BDLC module
are turned off, but the clocks in the MCU continue to run. Therefore, the message which wakes up the BDLC module from Stop and
the CPU from WAIT mode will be received correctly by the BDLC module. This is because very little time is required for the CPU
to turn the clocks to the BDLC module back on once the wakeup interrupt occurs.
NOTE
While the BDLC module will correctly receive a message which arrives when the BDLC module is
in Stop mode or Wait mode and the MCU is in WAIT mode, if the user enters this mode while a
message is being received, the data in the message will become corrupted. This is due to the steps
required for the BDLC module to resume operation upon exiting Stop mode or Wait mode, and its
subsequent resynchronization with the SAE J1850 bus.
• Digital Loopback
When a bus fault has been detected, the digital loopback mode is used to determine if the fault condition is caused by failure in the
node’s internal circuits or elsewhere in the network, including the node’s analog physical interface. In this mode, the input to the
digital filter is disconnected from the receive pin input (RXB). The input to the digital filter is then connected to the transmitter
output to form the loopback connection. The transmit pin (TXB) is negated and will always drive a passive state onto the bus. Digital
loopback mode is entered by setting the DLOOP bit in Section 20.7.3.3, BDLC Control Register 2 (DLCBCR2) - MBAR + 0x1304.
• Normal and Emulation Mode Operation
The BDLC module operates in the same manner in all Normal and Emulation Modes. All BDLC module registers can be read and
written except those that are reserved, unimplemented, or write once. The user must be careful not to unintentionally write a register
when using 16-bit writes in order to avoid unexpected BDLC module behavior.
• Special Mode Operation
Some aspects of BDLC module operation can be modified in special test mode. This mode is reserved for internal use only.