Freescale Semiconductor MPC5200B 13.3 Features summary, 13.4 Descriptors, 13.5 Tasks, 13.6 Memory Map/ Register Definitions

MPC5200B Users Guide, Rev. 1
13-2 Freescale Semiconductor
Features summary
NOTE
It is possible for the BESTComm DMA to produce misaligned word addresses on its Slave and Comm
bus. These accesses occur due to incorrect program code executed by the BestComm unit. Any
misaligned access will be incorrectly processed on the internal SRAM bus and the Comm bus.
The work around is to avoid using misaligned accesses. That is, BestComm program code must be
written such that misaligned word accesses will not occur.
BestComm DMA performs general purpose DMA transfers. Most data transactions are between the peripheral/interface (typically a FIFO)
and the system SDRAM.
BestComm allows up to 16 tasks to run simultaneously under the control of up to 32 DMA hardware requestors, user selectable from a possible
64 DMA request sources.
A hardware logic unit capable of basic logic operations (boolean arbitrary operations, shift, byte swap) plus some precoded CRC (CRC-16,
CRC-CCITT, CRC-32, Internet Checksum) is also integrated in the SDMA engine.
BestComm uses internal buffers to prefetch reads and post writes such that bursting is used whenever possible. This optimizes both internal
and external bus activity.
Speculative reads from system SDRAM may also be enabled to increase performance.
FIFO interfaces are implemented between the DMA and each peripheral/interface. As FIFOs are filled or emptied, automatic requests are
made to the DMA unit. Based on programmable water mark levels (called ALARM and GRANULARITY level), the DMA unit moves data
to and from the FIFOs. This method insures uninterrupted data movement at the given peripheral/interface rate.
13.3 Features summary
• A programmatic, deterministic capability for managing bus resources while servicing many data streams with individual latency
and processing requirements.
• Single cycle access of peripheral and memory data.
• Support for up to 16 simultaneously enabled tasks (channels).
• Support for up to 32 separate DMA requestors at a time, user selectable from a possible 64 DMA request sources.
• Support for operations with up to 12 sources, or 11 sources and 1 destination.
• Simultaneous 32-bit reads and writes.
• Checksum generation.
• Endian conversion.
• Chaining/Scatter-gather capability.
• Support for packet-based I/O protocols (limitation might be dictated by performance when too much control is implemented within
the task).
• External DMA Request.
• External DMA breakpoint.
13.4 Descriptors
The DMA controller interprets a series of descriptors that specifies a sequence of data movements and manipulations. A collection of these
descriptors is much like a program. The two types of descriptors are Loop Control Descriptors (LCDs) and Data Routing Descriptors (DRDs).
These descriptors allow a “for”-loop programming style for the SDMA engine.
The LCDs specify the index variables (memory pointers, byte counters, etc.) along with the termination and increment values, while the DRDs
specify the nature of the operation to perform.
13.5 Tasks
A task is a microcode program that embodies a desired function. An example could be to gather an ethernet frame, store it in memory and
interrupt the processor when done. The multi-channel DMA supports sixteen simultaneously enabled tasks. By dynamically swapping task
pointers in the task table, an unlimited number of tasks could be supported.
13.6 Memory Map/ Register Definitions
Memory organization is described in the register array pointed to by the Task Base Address Register (TaskBAR).
The TaskBAR identifies a location for a table of pointers to multi-channel DMA tasks (Task TABLE or Entry Table).