List of Tables
Tabl e Page
Number Number
MPC5200B Users Guide, Rev. 1
LOT-6 Freescale Semiconductor
14-1 Signal Properties ......................................................................................... .............................................................14-3
14-2 MII: Valid Encoding of TxD, Tx_EN and Tx_ER ..................................................................................................14-5
14-3 MII: Valid Encoding of RxD, Rx_ER and Rx_DV ..................................................................................... ............14-5
14-4 MMI Format Definitions ...................................................... ...................................................................................14-6
14-5 MII Management Register Set ..... ....................................................................................... ....................................14-6
14-6 Module Memory Map ............................................................................................................. ................................14-7
14-7 MIB Counters ..................................................................................................................................................... .....14-9
14-8 FEC ID Register .................................... .................................................................................. ..............................14-11
14-9 FEC Interrupt Event Register ................................................. ...............................................................................14-12
14-10 FEC Interrupt Enable Register ........................... ..................................................................................... ..............14-14
14-11 FEC Rx Descriptor Active Register ................................... ...................................................................................1 4-15
14-12 FEC Tx Descriptor Active Register ..................... ......................................................................................... ........14-15
14-13 FEC Ethernet Control Register ..................................................................................... .........................................14-16
14-14 FEC MII Management Frame Register ......................................... ........................................................................14-17
14-15 FEC MII Speed Control Register ....................................... ................................................................................... 14-18
14-16 Programming Examples for MII_SPEED Register ........................................................... ....................................14-19
14-17 FEC MIB Control Register ............................................................................................. .......................................14-19
14-18 FEC Receive Control Register ......................... ....................................................................................... ..............14-20
14-19 FEC Hash Register ......................................... ....................................................................................... ................14-21
14-20 FEC Tx Control Register .......................................................................... .............................................................14-21
14-21 FEC Physical Address Low Register ............. .................................................................................... ...................14-22
14-22 FEC Physical Address High Register .................................................................... ................................................14-23
14-23 FEC Opcode/Pause Duration Register ........................ ....................................................................................... ...14-23
14-24 FEC Descriptor Individual Address 1 Register ............................................... ......................................................14-24
14-25 FEC Descriptor Individual Address 2 Register ............................................... ......................................................14-24
14-26 FEC Descriptor Group Address 1 Register .............................................. .............................................................14-25
14-27 FEC Descriptor Group Address 2 Register .............................................. .............................................................14-25
14-28 FEC Tx FIFO Watermark Register .................... ....................................................................................... ............14-26
14-29 FIFO Interface Register Map .............. ...................................................................................... ............................14-27
14-30 FEC Rx FIFO Status Register .......................... ....................................................................................... ..............14-28
14-31 FEC Rx FIFO Control Register .............................................................. ...............................................................14-30
14-32 FEC Rx FIFO Last Read Frame Pointer Register ......................... ........................................................................14-30
14-33 FEC Rx FIFO Last Write Frame Pointer Register ............. ...................................................................................14-31
14-34 FEC Rx FIFO Alarm Pointer Register ...................... .................................................................................... ........14-32
14-35 FEC Rx FIFO Read Pointer Register ...................... ...................................................................................... ........14-32
14-36 FEC Rx FIFO Write Pointer Register ....... ..................................................................................... .......................14-33
14-37 FEC Reset Control Register ...................... ......................................................................................... ...................14-33
14-38 FEC Transmit FSM Register ................................................ .................................................................................14-34
14-39 ETHER_EN De-Assertion Affect on FEC ................................................................. ...........................................14-34
14-40 User Initialization (Before ETHER_EN) .................. ....................................................................................... .....14-35
14-41 Microcontroller Initialization (FEC) ......................... ......................................................................................... ...14-35
14-42 Receive Frame Status Word Format ............ ...................................................................................... ...................14-35
14-43 Transmit Frame Control Word Format ..... ....................................................................................... .....................14-36
14-44 Destination Address to 6-Bit Hash .................................................. ......................................................................14-41
14-45 PAUSE Frame Field Specification .................................................................... ....................................................14-43
14-46 Transmit Pause Frame Registers ............................. ...................................................................................... ........14-43
15-1 PSC Functions Overview ...................... ......................................................................................... .........................15-1
15-2 PSC Memory Map ................................................................................ ...................................................................15-3
15-3 Mode Register 1 (0x00) for UART Mode .................................................................................... ...........................15-5
15-4 Mode Register 1 (0x00) for SIR Mode ......................... ......................................................................................... .15-5
15-5 Mode Register 1 (0x00) for other Modes .......................................................................... ......................................15-5
15-6 Parity Mode/Parity Type Definitions ...................... .................................................................................... ............15-6
15-7 Mode Register 2 (0x00) for UART / SIR Mode ......................... ............................................................................15-6
15-8 Mode Register 2 (0x00) for other Modes .......................................................................... ......................................15-6