MPC5200B Users Guide, Rev. 1
20-30 Freescale Semiconductor
Functional Description
• Digital Loopback Multiplexer
The Digital Loopback Multiplexer connects the input of the receive digital filter (See Figure 20-12) to either the transmit signal out
to the pad (TXB) or the receive signal from the pad (RXB), depending on the state of the DLOOP bit in BDLC Control Register 2
register.
• State Machine
All of the functions associated with performing the protocol are executed or controlled by the State Machine. The State Machine is
responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The following sections
describe the BDLC module’s actions in a variety of situations.
• 4X Mode
The BDLC module can exist on the same J1850 bus as modules which use a special 4X (41.6 kbps) mode of J1850 VPW operation.
The BDLC module can transmit and receive messages in 4X mode, if the 4XE bit is set in BDLC Control Register 2. If the 4XE bit
is not set in the BDLC Control Register 2, any 4X message on the J1850 bus is treated as noise by the BDLC module and is ignored.
Likewise, 4X messages transmitted on the SAE J1850 bus when the BDLC module is in normal mode will be interpreted as noise
on the network by the BDLC module.
• Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC module does allow for a special “Block Mode” of operation of the
receiver. As far as the BDLC module is concerned, a Block Mode message is simply a long J1850 frame that contains an indefinite
number of data bytes. All of the other features of the frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a Block Mode transmission must first inform all other nodes on the network that this is about to
happen. This is usually accomplished by sending a special predefined message.
• Transmitting a Message in Block Mode
A Block mode message is transmitted inherently by simply loading the bytes one by one into the BDLC Data Register register until
the message is complete. The programmer should wait until the TDRE flag is set prior to writing a new byte of data into the BDLC
Data Register register. The BDLC module does not contain any predefined maximum J1850 message length requirement.
20.8.4 Transmitting A Message
The design of the BDLC module enables the user to easily handle message reception and message transmission separately. This can greatly
simplify the communication software, as all received messages can be handled virtually the same, regardless of their origin.
This chapter will therefore describe only the steps necessary for transmitting a message, and will not address the resulting reception of that
message by the BDLC module. Message reception is described in Section 20.8.5, Receiving A Message. Later sections will deal with
transmitting and receiving In-Frame Responses on the SAE J1850 bus.

20.8.4.1 BDLC Transmission Control Bits

There is only one BDLC module control bit which is used when transmitting a message onto the SAE J1850 bus. This bit, the Transmit End
of Data (TEOD) bit, is set by the user to indicate to the BDLC module that the last byte of that part of the message frame has been loaded into
the BDLC Data Register. The TEOD bit, located in BDLC Control Register 2, is also used when transmitting an In-Frame Response (IFR),
but that usage is described in Section 20.8.6, Transmitting An In-Frame Response (IFR). Setting the TEOD bit indicates to the BDLC module
that the last byte written to the BDLC Data Register is the final byte to be transmitted, and that following this byte a CRC byte and EOD
symbol should be transmitted automatically. Setting the TEOD bit will also inhibit any further TDRE interrupts until TEOD is cleared. The
TEOD bit will be cleared on the rising edge of the first bit of the transmitted CRC byte, or if an error or loss of arbitration is detected on the bus.
• BDLC Data Register
The BDLC Data Register is a double-buffered register which is used for handling the transmitted and received message bytes.Bytes
to be transmitted onto the SAE J1850 bus are written to the BDLC Data Register, and bytes received from the bus by the BDLC
module are read from the BDLC Data Register. Since this register is double buffered, bytes written into it cannot be read by the
CPU. If this is attempted, the byte which is read will be the last byte placed in the BDLC Data Register by the BDLC module, not
the last byte written to the BDLC Data Register by the CPU. For an illustration of the BDLC Data Register, refer to Section 20.7.3.4,
BDLC Data Register (DLCBDR) - MBAR + 0x1305.
• Transmitting a Message with the BDLC
To transmit a message using the BDLC module, the user just writes the first byte of the message to be transmitted into the BDLC
Data Register, initiating the transmission process. When the TDRE status appears in the BDLC State Vector Register, the user writes
the next byte into the BDLC Data Register. Once all of the bytes have been loaded into the BDLC Data Register, the user sets the
TEOD bit, and the BDLC module completes the message transmission. What follows is an overview of the basic steps required to
transmit a message onto an SAE J1850 network using the BDLC module. For an illustration of this sequence, refer to Figure20-13.