Freescale Semiconductor MPC5200B 10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) MBAR + 0x3844

Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-31
10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) —MBAR + 0x3844
Bits Name Description
0:31 FIFO_Data_Word This is the data port to the FIFO. Reading from this location will “pop” data from the
FIFO, writing data will “push” data into the FIFO. During normal operation the
Multi-Channel DMA controller will be pushing data here. The PCI controller will pop
data for transmission from a dedicated peripheral port, so the user program should not
be reading here. At reset any uninitialized random 32 bit value is read at this address.
A FIFO reset must be always performed before first accessing the FIFO.
Note: Only full 32-bit accesses are allowed. If all Byte enables are not asserted when
accessing this location, FIFO data will be corrupted.
msb 012345678 9 101112131415
RReserved RXW UF OF FR Full Alarm Empty
Wrwc rwc rwc
RESET 0 00000000 1 0 0001 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
RReserved
W
RESET 0 00000000 0 0 000 0 0
Bits Name Description
0:8 Reser ved Unused. Software should write zero to these bits.
9 Receive Wait
Condition
(RXW)
This flag bit indicates that the ipf_rcv bus is incurring wait states because there is not enough
room in the FIFO to accept the data without causing overflow. This bit will cause the error
outputs (fifoError, ipf_rcv_error, ipf_xmit_error) to assert unless the RXW_MASK bit in the
FIFO Control register is set. Resetting the FIFO will clear this condition and the flag bit is
cleared by writing a one to its bit position.
10 UnderFlow
(UF)
This flag bit indicates that the read pointer has surpassed the write pointer. In other words
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
11 OverFlow
(OF)
This flag bit indicates that the write pointer has surpassed the read pointer. In other words
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
12 Frame Ready
(FR)
The FIFO has a complete Frame of data ready for transmission. This module
does not provide support for Data Framing applications, so this bit should be ignored.
13 Full The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the
state of the FIFO.
14 Alarm When the FIFO pointer is at or below the Alarm “watermark”, as written by the user according
to the Alarm and Control registers settings, this bit is set, automatically signalling to the DMA
engine the need to re-fill the FIFO. By writing a ‘1’ to this bit software can enforce a
re-evaluation of the ‘alarm’ condition.
15 Empty The FIFO is empty. This is not a sticky bit or error condition.
16:31 Reserved Unused. Software should write zero to these bits.