Freescale Semiconductor MPC5200B manual D

D
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor A-3
Context synchronization. . . . An operation that ensures:
• all instructions in execution complete past the point where they can produce an exception
• all instructions in execution complete in the context in which they began execution
• all subsequent instructions are fetched and executed in the new context.
. . . . . . . . . . . . . . . . . . . . . . . Context synchronization may result from executing specific instructions (such as isync or rfi) or when certain
events occur (such as an exception).
COP. . . . . . . . . . . . . . . . . . . . Common On-chip Processor
Copy-back. . . . . . . . . . . . . . . An operation in which modified data in a cache block is copied back to memory.
CP . . . . . . . . . . . . . . . . . . . . . Communications Processor
CPI . . . . . . . . . . . . . . . . . . . . Common Part Indicators
CPM . . . . . . . . . . . . . . . . . . . Communications Processor Module
CPS. . . . . . . . . . . . . . . . . . . . Cells Per Slot
CQ. . . . . . . . . . . . . . . . . . . . . Completion Queue
CR. . . . . . . . . . . . . . . . . . . . . Condition Register
CRC . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check—Error detecting codes that generate a parity check.
Critical-data first. . . . . . . . . . An aspect of burst access that lets requested data (typically a word or double word) in a cache block be
transferred first.
CS . . . . . . . . . . . . . . . . . . . . . Chip Select, or Convergence Sublayer
CSC. . . . . . . . . . . . . . . . . . . . Chip Select Controller—LocalPlus Controller
CSMA. . . . . . . . . . . . . . . . . . Carrier Sense Multiple Access
CT. . . . . . . . . . . . . . . . . . . . . Connection Table
CTL, ctl. . . . . . . . . . . . . . . . . Control
CTR. . . . . . . . . . . . . . . . . . . . Count Register
CUMB. . . . . . . . . . . . . . . . . . Check Unused Mask Bits
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DABR. . . . . . . . . . . . . . . . . . Data Address Breakpoint Register
DAR . . . . . . . . . . . . . . . . . . . Data Address Register
DDR . . . . . . . . . . . . . . . . . . . Dual-Data Rate
DEC . . . . . . . . . . . . . . . . . . . Decrementer ( register)
Denormalized number. . . . . . A non-zero floating-point number whose exponent has:
a reserved value, usually the format's minimum, and
whose explicit or implicit leading significant bit is 0.
Direct-mapped cache . . . . . . A cache in which each main memory address can appear in only one location within the cache, operates more
quickly when the memory request is a cache hit.
Direct-store. . . . . . . . . . . . . . Interface available only on microprocessors that use the PowerPC architecture; supports direct-store devices
from the POWER architecture. When the T-bit of a segment descriptor is set, the descriptor defines the region
of memory to be used as a direct-store segment.
This facility is being phased out of the architecture and is not likely be supported in future devices. Therefore, software should not depend on
it and new software should not use it.
DMA. . . . . . . . . . . . . . . . . . . Direct Memory Access
DPLL . . . . . . . . . . . . . . . . . . Digital Phase-Locked Loop
DPR. . . . . . . . . . . . . . . . . . . . Dual-Port RAM
DR. . . . . . . . . . . . . . . . . . . . . Data Register
DRAM . . . . . . . . . . . . . . . . . Dynamic Random Access Memory
DSI . . . . . . . . . . . . . . . . . . . . Data Storage Interrupt
DSISR. . . . . . . . . . . . . . . . . . DSI Source Register—a register used for determining the source of a DSI exception.
DTLB . . . . . . . . . . . . . . . . . . Data Translation Lookaside Buffer
DTV . . . . . . . . . . . . . . . . . . . Digital TV
DWPCI . . . . . . . . . . . . . . . . . designware PCI—synopsys designware compone nt