MPC5200B Users Guide, Rev. 1
5-8 Freescale Semiconductor
MPC5200B Clock Domains
Figure 5-3 shows the clock relationships for the SDRAM Controller.

Figure 5-3. Timing Diagram—Clock Waveforms for SDRAM and DDR Memories

The XLB is 64bits and the SDRAM external bus is 32bits. When SDR (single data rate) SDRAM memory is used, the XLB bandwidth is only
half utilized. When DDR (dual data rate) memory is used, the XLB bandwidth is fully used on SDRAM transactions.
MPC5200B supplies 2 external memory clocks as part of the SDRAM interface:
• MEM_MEMCLK
•MEM_MEMCLK
MEM_MEMCLK and MEM_MEMCLK are always the same frequency as XLB clock. SDR memory uses MEM_MEMCLK only; DDR
memory uses both MEM_MEMCLK and MEM_MEMCLK.
5.3.5 IPB Clock Domain
IPB clock can run at the same frequency as XLB clock, or 1/2 the frequency. BestComm runs at the IPB clock frequency as does all IPB
control register access logic.
5.3.6 PCI Clock Domain
The PCI bus clock is the fundamental frequency of the PCI bus interface. The PCI clock can run at the XLB clock frequency, or 1/2 the XLB
clock frequency, or 1/4 the XLB clock frequency. The PCI clock cannot be faster than IPB Clock.

Table5-7. SDRA M Memory Controller Clock Domain

Bits Description
mem_clk mem_clk is always the same frequency as xlb_clk.
mem_2x_clk,
mem_2x_clk
These internal clocks are twice the frequency of xlb_clk and are used to add more resolution to
SDRAMC control signals
mem2x1x_clk
(becomes
mem_rd_clk)
This is the source of the internal memory read clock. It always operates at the memory data rate,
1x mem_clk for SDR, 2x mem_clk for DDR. The physical circuit path of mem2x1x_clk is matched
as closely as possible to the on-chip portion of the memory clock output and the read data input;
a tapped delay chain is used to match off-chip portions of the memory clock and read data path.
mem_2x_clk
mem_2x_clk
mem2x1x_clk
MEM_MEMCLK, mem_clk

DDR SDRAM Memory Clocks

mem_2x_clk
MEM_MEMCLK, mem_clk
xlb_clk

SDR SDRAM Memory Clocks

mem_2x_clk
mem2x1x_clk
xlb_clk