Freescale Semiconductor MPC5200B manual Reserved

MPC5200B Users Guide, Rev. 1
10-50 Freescale Semiconductor
Functional Description
Figure 10-4. Contents of the AD Bus During Address Phase of a Type 0 Configuration Transaction
Address bits [10:8] identify the target function and bits AD[7:2] select one of the 64 configuration dwords within the target function’s
configuration space. For Type 0 configuration transactions, the target device’s IDSEL pin must be asserted. The upper 21 address lines are
commonly used as IDSELs since they are not used during the address phase of a type 0 configuration transaction.
If the target bus is a bus that is subordinate to the local PCI bus (bus 0), the configuration transaction is still initiated on bus 0, but indicates
that none of the devices on this bus are the target of the transaction. Rather, only PCI-to-PCI bridges residing on the bus should pay attention
to the transaction because it targets a device on a bus further out in the hierarchy beyond a PCI-to-PCI bridge that is attached to the local PCI
bus (bus 0). This is accomplished by initiating a Type 1 configuration transaction (setting AD[1:0] to 01b during the address phase). This
pattern instructs all functions other than PCI-to-PCI bridges that the transaction is not for any of them. Figure 10-5 illustrates the contents of
the AD bus during the address phase of the Type 1 configuration access.
Figure 10-5. Contents of the AD Bus During Address Phase of a Type 1 Configuration Transaction
During the address phase of a Type 1 configuration access, the information on the AD bus if formatted as follows:
• AD[1:0] contain a 01b, identifying this as a Type 1 configuration access.
• AD[7:2] identifies one of 64 configuration dwords within the target devices’s configuration space.
• AD[10:8] identifies one of the eight functions within the target physical device.
• AD[15:11] identifies one of 32 physical devices. This field is used by the bridge to select which device’s IDSEL line to assert.
• AD[23:16] identifies one of 256 PCI buses in the system.
• AD[31:24] are reserved and are cleared to zero.
During a Type 1 configuration access, PCI devices ignore the state of their IDSEL inputs. When any PCI-to-PCI bridge latches a Type 1
configuration access (command = configuration read or write and AD[1:0] = 01b) on its primary side, it must determine whether the bus
number field on the AD bus matches the number of its secondary bus or if it’s within the range of its subordinate buses. If the bus number
matches, it should claim and pass the configuration access onto its secondary bus as a Type 0 configuration access, decoding the device
number to select one of the IDSEL lines. If the bus number isn’t equal to its secondary bus, but is within the range of buses that are subordinate
to the bridge, the bridge claims and passes that access through as a Type 1 access.
10.4.1.5.4 Address decoding
For positive address decoding, an address hits when the address on the address bus matches an assigned address range. Multiple devices on
the same PCI bus may use positive address decoding, though there can not be any overlap in the assigned address ranges.
For subtractive address decoding, an address hits when the address on the address bus does not match any address range for any of the PCI
devices on the bus. Only one device on a PCI bus may use subtractive address decoding, and its use is optional.
31 11 10 87 2 1 0
Reserved Function
Number
DW
Number 00
Target configuration doubleword number
31 11 10 87 210
Reserved Function
Number
DW
Number 01
Doubleword number in the device’s configuration space
24 23 1615
Device
Number
Bus
Number