Freescale Semiconductor MPC5200B 10.4.5 XL bus Target Interface

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-57
During the data phase, AD[31:0] contain the Special Cycle message and an optional data field. The Special Cycle message is encoded on the
16 least significant bits (AD[15:0]) and the optional data field is encoded on the most significant bits (AD[31:16]). The Special Cycle message
encodings are assigned by the PCI SIG Steering Committee. The current list of defined encodings are provided in Table10-9.
10.4.4.3 Transaction Termination
If the PCI cycle Master Aborts, interface will return 0xFFFFFFFF as read data, but complete without error. It will issue an interrupt to the
internal interrupt controller if enabled.
For abnormal transaction termination during an XL bus-initiated transaction (unsupported transfer types, retry limit reached, or target abort),
an error is generated. It will issue an interrupt to the MPC5200B Interrupt controller if such interrupts are enabled.
Transfers that cross the 32-bit boundary (greater than 4 bytes) to a PCI non-memory address range result in a transfer error. The space is
defined as nonmemory if the IO/M# configuration bit associated with that window is programmed “0”.
10.4.5 XL bus Target Interface
• The target interface can issue target abort, target retry, and target disconnect terminations.
• The target interface does NOT support fast back-to-back cycles.
• No support of dual address cycles as a PCI target.
• Target transactions are not snooped by the processor.
• Medium device selection timing
• Three 32-byte buffers enhance data throughput.
The XL Bus Target Interface provides access for external PCI masters to two windows of MPC5200B address space. Target Base Address
Translation Registers 0 and 1 allow the user to map PCI address hits on MPC5200B PCI Base Address Registers to areas in the internal address
space. All of these registers must be enabled for this interface to operate.
Upon detection of a PCI address phase, the PCI controller decodes the address and bus command to determine if the transaction is for local
memory (BAR0 or BAR1hit). If the transaction falls within MPC5200B PCI space (a PCI memory space only), the PCI Controller target
interface asserts DEVSEL, latches the address, decodes the PCI bus command, and forwards them to the internal control unit. On writes, data
is forwarded along with the byte enables to the internal gasket. On reads, four bytes of data are provided to the PCI bus and the byte enables
determine which byte lanes contain meaningful data. If no byte enables are asserted, MPC5200B completes a read access with valid data and
completes a write access by discarding the data internally. All target transactions will be translated into XL bus master transactions.
There are two address translation registers that must be initialized before data transfer can begin. These address registers correspond to BAR0
and BAR1 in MPC5200B PCI Type 00h Configuration space register (PCI space). When there is a hit on MPC5200B PCI base address ranges
(0 or 1), the upper bits of the address are written over by this register value to address some space in MPC5200B. One 256Kbyte base address
range (BAR0) maps to non-prefetchable local memory and one 1Gbyte range (BAR1) targeted to prefetchable memory.
Table 10-9. Special Cycle Message Encodings
AD[15:0] Message
0x0000 SHUTDOWN
0x0001 HALT
0x0002 x86 architecture-specific
0x0003-0xFFFF reserved
Table10-10. Unsupported XL Bus Transfers
XL Bus Transaction PCI Address Space
Burst (32-byte) Nonmemory
> 4 byte Single Beat Nonmemory
4 byte Single Beat at a[29:31] 001, 010, or 011 Nonmemory
3 byte Single Beat at a[29:31] 010 or 011 Nonmemory
2 byte Single Beat at a[29:31] 011 Nonmemory