Freescale Semiconductor MPC5200B 16.1.1.2.1 Bus Grant, 16.1.1.2.2 Parking Modes, 16.1.1.4.1 Timer Functions

MPC5200B Users Guide, Rev. 1
16-2 Freescale Semiconductor
Overview
Multiple masters at level 0 will only be able to perform one tenure before the bus is passed to the next master at level 0 using the LRU
algorithm.
The priority level of each master may be changed while the arbiter is running. This allows dynamic changes in priority such as an aging
scheme. It is possible for the e300 core to control priority by enabling the Master Priority Enable bits for a master. This causes the priority to
be determined from the Master N Priority bits in the Arbiter Master N Priority Register. The e300 core then may write this register to set the
master's priority.
16.1.1.2 Bus Grant Mechanism
16.1.1.2.1 Bus Grant
The Bus Grant mechanism will generate the address bus grant signals to the masters using the signals from the prioritization function as well
as the internal XL bus signals (ts_b, aack_b, ta_b, tt[0:4], artry, tbst_b, tea_b, dbb_b). It will also generate required indicators of state to the
prioritization and watchdog functions.
The Bus Grant mechanism will enforce a one level address pipeline, if pipelining is enabled (via the PLDIS bit in the Arbiter Configuration
Register). The critical condition is that before a third address tenure is granted, the first tenure (address, and if needed, data) must be
completed. The arbiter will assert bus grant to a master when the master is requesting, or if parking is enabled, and the one level pipeline
condition is met.
16.1.1.2.2 Parking Modes
The Bus Grant mechanism will support the No Parking, Park on Programmed Master, and Park on Last Master bus parking modes. When in
No Parking Mode, the arbiter will not assert bus grant when there are no masters asserting bus request. In Park on Programmed Master Mode,
the arbiter will assert bus grant to the master indicated in the Select Parked Master bits (Arbiter Configuration Register, SP[2:0] bits) when
no masters are asserting bus request, and the one level pipeline will not be violated. In Park on Last Master Mode, the arbiter will assert bus
grant to the last master granted the bus when no masters are asserting bus request, and the one level pipeline will not be violated.
16.1.1.3 Configuration, Status, and Interrupt Generation
This block provides a set of status and configuration registers as well as interrupt generation for enabled interrupt conditions. These registers
are detailed in the register section below. Some registers have reserved (unused, undefined) bits. These bits will always read as 0, and if
written, should be written to 0 for future software compatibility.
16.1.1.4 Watchdog Functions
16.1.1.4.1 Timer Functions
There are three watchdog timers for address tenure, data tenure, and bus activity time out. Each has a programmable timer count and can be
disabled. A timer time-out will set a status bit and trigger an interrupt if that interrupt is enabled.
The address tenure watchdog is a 32-bit timer. If an AACK is not detected by the programmed number of clocks after bus grant is accepted,
the address watchdog timer will expire and the arbiter will issue AACK. The related data tenure will be terminated with TEA. The arbiter will
set the Address Tenure Time-out Status bit in the Arbiter Status Register and issue an interrupt if that interrupt is enabled.
The upper 28-bits of address tenure time-out are programmed via the Address Tenure Time-out Register. The lower 4 bits are always 0xF.
The data tenure watchdog is a 32-bit timer. If a data tenure is not terminated, the data watchdog timer will expire and the arbiter will issue
TEA. The arbiter will set the Data Tenure Time-out Status bit in the Arbiter Status Register and issue an interrupt if that interrupt is enabled.
Address Time-out (32 bits) = {Address Tenure Time-out Register (28-bits), 0xF}
Data Time-out (32 bits) = {Data Tenure Time-out Register (28-bits), 0xF}
NOTE
Enabling the data time-out will also enable the address time-out. This is required to prevent a data
time-out before an AACK assertion.
The bus activity watchdog is a 32-bit timer. If no bus activity (no assertion of DBB or ABB) is detected by the programmed number of clocks,
the bus activity watchdog timer will expire and the arbiter will set the Bus Activity Time-out Status bit in the Arbiter Status Register and issue
an interrupt if that interrupt is enabled.
For any TEA assertion (from a watchdog time-out, or other source), a Machine Check exception will result in the e300 core. See the XLB
Arbiter interrupt enablement recommendations below for the Arbiter Interrupt Enable Register. For more information on the Machine Check
exception, see the 603e Users’ Manual, Section 4.5.