Intel 21555 user manual Parity Errors, Parity Error Responses Sheet 1

Error Handling

12.2Parity Errors

The 21555 checks, forwards, and generates parity on both the primary and secondary buses. When forwarding transactions, the 21555 forwards the data parity condition as queued, whether it is bad parity or good parity. Table 29 describes the 21555’s responses to parity errors.

Table 29. Parity Error Responses (Sheet 1 of 3)

Type of	Type of	PER†		Action Taken
Error	Transaction	PS
				• Responds normally to transaction.
		0 —		• Sets primary Detected Parity Error bit.
	Primary Bus			• Forwards transaction with correct parity.
	Transaction			• Does not respond to transaction.
		1 —		• Asserts p_serr_l (when enabled).
Address				• Sets primary Detected Parity Error bit.
Parity Error				• Responds normally to transaction.
		—	0	• Sets secondary Detected Parity Error bit.
	Secondary			• Forwards transaction with correct parity.
	Bus
				• Does not respond to transaction.
	Transaction
		—	1	• Asserts s_serr_l (when enabled).
				• Sets secondary Detected Parity Error bit.
		0 —		• Forwards transaction with parity error.
				• Sets primary Detected Parity Error bit.
	Downstream
				• Forwards transaction with parity error.
	Posted Write
		1 —		• Sets primary Detected Parity Error bit.
Data Parity				• Asserts p_perr_l.
				Trans
Error on		0 —
Primary				action completes normally on primary bus.
Bus
	Upstream	1 —		• Transaction completes on primary bus.
				• Sets primary Data Parity Detected bit when p_perr_l is asserted.
	Posted Write
				• Transaction completes on primary bus.
		1 1		• Sets primary Data Parity Detected bit when p_perr_l is asserted.
				• Asserts s_serr_l when no parity error detected on secondary bus.

†PER: Parity Error Response bit (Primary Secondary).

21555 Non-Transparent PCI-to-PCI Bridge User Manual 107