Intel 21555 Primary and Secondary Command Registers, Offsets Primary Command Secondary Command

List of Registers

16.5.2Primary and Secondary Command Registers

The register types in this section have separate registers for the primary and secondary interfaces. However, the register description is given once, and applies to both the primary and secondary configuration registers. The primary register controls behavior on the primary interface only, and the secondary register controls behavior on the secondary interface only.

Table 61. Primary and Secondary Command Registers (Sheet 1 of 2)

	Offsets			Primary Command	Secondary Command
	Primary byte			05:04h	45:44h
	Secondary byte			45:44h	05:04h
	Bit	Name	R/W	Description
				Controls response to I/O transactions on the corresponding interface.
0		I/O Space	R/W	• When 0, the 21555 does not respond to I/O transactions.
		Enable		• When 1, the 21555 response to I/O transactions is enabled.
				• Reset value is 0
				Controls response to memory transactions on the corresponding
				interface.
1		Memory	R/W	• When 0, the 21555 does not respond to memory transactions.
		Space Enable
				• When 1, the 21555 response to memory transactions is enabled.
				• Reset value is 0.
				Controls 21555's ability to initiate memory and I/O transactions on the
				corresponding interface. Initiation of configuration transactions is not
				affected.
2		Master Enable	R/W	• When 0, the 21555 does not initiate memory or I/O transactions.
				• When 1, the 21555 is enabled to operate as an initiator.
				• Reset value is 0.
3		Special Cycle	R	The 21555 ignores special cycle transactions, so this bit is read only and
		Enable		returns 0.
				This bit controls the ability of the 21555 to generate Memory Write and
				Invalidate (MWI) bus commands as a master on the corresponding
		Memory Write		interface.
				• When 0, Disables use of MWI bus commands (uses Memory Write
4		and Invalidate	R/W
		Enable		commands instead).
				• When 1, Enables use of MWI bus commands.
				• Reset value is 0
5		VGA Snoop	R	Reads only as 0 to indicate the 21555 does not respond to VGA palette
		Enable		writes.
				Controls the response of the 21555 when a parity error is detected on the
				corresponding interface.
				• When 0, the 21555 does not assert PERR#, nor does it set the Data
				Parity Reported bit in the appropriate Primary or Secondary Status
		Parity Error		registers. The 21555 does not report address parity errors by
6			R/W	asserting SERR#.
		Response
				• When 1, the 21555 drives PERR# and conditionally sets the Data
				Parity Reported bit in the Primary or Secondary Status register when
				a data parity error is detected. The 21555 allows SERR# assertion
				when address parity errors are detected.
				• Reset value is 0.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 149