Error Handling

Table 29. Parity Error Responses (Sheet 3 of 3)

Type of

Type of

PER

Action Taken

Error

Transaction

PS

 

 

 

 

 

 

 

 

— 0

Transaction completes normally on secondary bus.

 

 

 

 

 

 

 

1

• Transaction completes on secondary bus.

 

Downstream

• Sets secondary Data Parity Detected bit when s_perr_l is asserted.

 

 

 

 

Posted Write

 

 

 

 

 

 

 

• Transaction completes on secondary bus.

 

 

 

 

 

 

1 1

Sets secondary Data Parity Detected bit when s_perr_l is asserted.

 

 

 

 

• Asserts p_serr_l when no parity error detected on primary bus.

 

 

 

 

 

 

 

0

• Forwards transaction with parity error.

 

 

• Sets secondary Detected Parity Error bit.

 

 

 

 

 

Upstream

 

 

 

 

 

 

 

• Forwards transaction with parity error.

 

Posted Write

 

 

 

 

 

 

 

 

 

1

Sets secondary Detected Parity Error bit.

 

 

 

 

Asserts s_perr_l.

 

 

 

 

 

 

— 0

Transaction completes normally on secondary bus.

 

 

 

 

 

 

 

1

• Transaction completes normally on secondary bus.

 

Downstream

• Sets secondary Data Parity Detected bit when s_perr_l is asserted.

 

 

 

 

Delayed

 

 

 

 

 

 

 

• Transaction completes normally on secondary bus.

 

Write

 

 

 

 

 

• Sets secondary Data Parity Detected bit when s_perr_l is asserted.

 

 

1 1

 

 

• Asserts p_perr_l when returning p_trdy_l to initiator on primary

 

 

 

 

 

 

 

 

 

bus (for both CSR and BAR forwarding mechanisms).

 

 

 

 

Data Parity

 

— 0

Transaction completes normally on secondary bus.

 

 

 

 

 

 

 

 

• Returns TRDY# (and STOP# if multiple data phases requested).

Error on

Upstream

 

 

Secondary

Delayed

1

Transaction not forwarded.

Bus

Write

• Sets secondary Parity Error Detected bit.

 

 

 

 

 

 

 

 

Asserts s_perr_l.

 

 

 

 

 

 

 

 

 

• Returns read data with bad parity to initiator (for both CSR and BAR

 

 

0

 

forwarding mechanisms).

 

 

 

 

• Sets secondary Parity Error Detected bit.

 

Downstream

 

 

 

 

 

 

 

• Returns read data with bad parity to initiator (for both CSR and BAR

 

Delayed

 

 

 

 

 

 

forwarding mechanisms).

 

Read

 

 

 

 

 

 

Sets secondary Parity Error Detected bit.

 

 

1

 

 

 

 

• Sets secondary Data Parity Detected bit.

 

 

 

 

Asserts s_perr_l.

 

 

 

 

 

 

 

Upstream

 

 

 

Delayed

The 21555 is returning data, all action is taken by initiator.

 

 

 

Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

• Writes the data normally.

 

 

• Sets the secondary Parity Error Detected bit.

 

Configuration

 

 

 

 

 

 

 

 

Register or

 

 

• Writes the data normally.

 

CSR Write

1

Sets the secondary Parity Error Detected bit.

 

 

 

 

 

 

Asserts s_perr_l.

 

 

 

 

 

 

 

Configuration

 

 

 

Register or

Returns read data normally.

 

 

 

CSR Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PER: Parity Error Response bit (Primary Secondary).

21555 Non-Transparent PCI-to-PCI Bridge User Manual

109

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Image 109
Intel 21555 user manual Parity Error Responses Sheet 3, Asserts sperrl

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