Intel 21555 Secondary Bus Arbitration Using an External Arbiter, Arbiter Control Register

Arbitration

The 21555’s internal arbiter may be programmed to park the secondary PCI bus either at the last master to use the bus, or always on the 21555. In the former case, an initiator's secondary bus grant remains asserted unless and until another initiator has asserted its secondary bus request. In the latter case, when no requests are asserted once a transaction has been initiated, the bus grant is withdrawn from the last master and is asserted internally to the 21555. After reset, the internal arbiter always parks the secondary bus at the 21555.

For secondary bus internal arbitration, 21555 internal arbitration signal pairs [5:8] are disabled for 66 MHz operation.

10.4.2Secondary Bus Arbitration Using an External Arbiter

The internal arbiter is disabled when pr_ad[7] is detected low during reset. An external arbiter must then be used. When the internal arbiter is disabled, the 21555 redefines two pins to be external request and grant pins. The s_gnt_l[0] pin is redefined to be the 21555's external request pin, since it is an output. The s_req_l[0] pin is redefined to be the external grant pin, since it is an input. The unused secondary bus grant outputs, s_gnt_l[8:1], are driven high. Unused secondary bus request inputs, s_req_l[8:1], should be pulled high through external resistors.

When s_req_l[0] is asserted and the 21555 has not asserted s_gnt_l[0], the 21555 parks the s_ad, s_cbe_l, and s_par pins by driving them to valid logic levels. The 64-bit extension signals on the 21555 are not bus parked.

Table 25. Arbiter Control Register

Bit	Name	R/W	Description
			Each bit controls whether a secondary bus master is assigned to the high
			priority arbiter ring or the low priority arbiter ring. Bits [8:0] correspond to
			request inputs s_req_l[8:0], respectively. Bit [9] corresponds to the internal
9:0	Arbiter Control	R/W	21555 secondary bus request.
			When 0, Indicates that the master belongs to the low priority group.
			When 1: Indicates that the master belongs to the high priority group.
			Reset value: 10 0000 0000b.
			Controls whether the 21555 parks on itself or on the last master to use the
			bus.
	Bus Parking		When 0, During bus idle, the 21555 parks the bus on the last master to use
10		R/W	the bus.
	Control
			When 1: During bus idle, the 21555 parks the bus on itself. The bus grant is
			removed from the last master and internally asserted to the 21555.
			Reset value: 0b.
15:11	Reserved	R	Reserved. Returns 0 when read.

100 21555 Non-Transparent PCI-to-PCI Bridge User Manual