Intel 21555 user manual Primary PCI Bus Interface Signals Sheet 2, Ppar, Preql, Pstopl, Ptrdyl

Signal Descriptions

Table 6. Primary PCI Bus Interface Signals (Sheet 2 of 2)

Signal Name	Type	Description
		Primary PCI interface parity. Signal p_par carries the even parity of the 36 bits of
		p_ad[31:0] and p_cbe_l[3:0] for both address and data phases. Signal p_par is
		driven by the same agent that drives the address (for address parity) or the data (for
		data parity). Signal p_par contains valid parity one clock cycle after the address is
		valid (indicated by assertion of p_frame_l), or one clock cycle after the data is valid
p_par	TS	(indicated by assertion of p_irdy_l for write transactions and p_trdy_l for read
		transactions). Signal p_par is tristated one clock cycle after the p_ad lines are
		tristated.
		The device receiving data samples p_par as an input to check for possible parity
		errors. When the primary PCI bus is idle, the 21555 drives p_par to a valid logic
		level when p_gnt_l is asserted (one clock cycle after the p_ad bus is parked).
p_req_l		Primary PCI bus REQ#. Signal p_req_l is asserted by the 21555 to indicate to the
	TS	primary bus arbiter that it wants to start a transaction on the primary bus. Signal
		p_req_l is tristated during the assertion of chip reset.
		Primary PCI interface STOP#. Signal p_stop_l is driven by the target of a
		transaction, indicating that the target is requesting the initiator to stop the transaction
		on the primary bus.
		• When p_stop_l is asserted in conjunction with p_trdy_l and p_devsel_l
		assertion, a disconnect with data transfer is being signaled.
p_stop_l	STS	• When p_stop_l and p_devsel_l are asserted, but p_trdy_l is deasserted, a
		target disconnect without data transfer is being signaled. When this occurs on
		the first data phase, that is, no data is transferred during the transaction, this is
		referred to as a target retry.
		• When p_stop_l is asserted and p_devsel_l is deasserted, the target is
		signaling a target abort.
		Upon completion of a transaction, p_stop_l is driven to a deasserted state for one
		clock cycle and is then sustained by an external pull-up resistor.
		Primary PCI interface TRDY#. Signal p_trdy_l is driven by the target of a
		transaction to indicate the target's ability to complete the current data phase on the
		primary PCI bus.
		During a write transaction, assertion of p_trdy_l indicates that the target is able to
p_trdy_l	STS	accept write data for the current data phase.
		During a read transaction, assertion of p_trdy_l indicates that the target is driving
		valid read data on the p_ad bus. Once asserted during a given data phase, p_trdy_l
		is not deasserted until the data phase completes.
		Upon completion of a transaction, p_trdy_l is driven to a deasserted state for one
		clock cycle and is then sustained by an external pull-up resistor.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 25