Intel 21555 user manual Chip Control 0 Register Sheet 2, Serr#

List of Registers

Table 77. Chip Control 0 Register (Sheet 2 of 4)

This register may be preloaded by serial ROM or programmed by the local processor before host configuration.

•Primary byte offset: CD:CCh

•Secondary byte offset: CD:CCh

Bit	Name	R/W	Description
			Sets the maximum number of PCI clock cycles that the 21555 waits for an
			initiator on the secondary bus to repeat a delayed transaction request. The
			counter starts when the delayed transaction completion is ready to be
			returned to the initiator. When the initiator has not repeated the transaction
	Secondary		at least once before the counter expires, the 21555 discards the delayed
			transaction from its queues.
3	Master	R/W
			• When 0, the secondary master timeout counter is 215 PCI clock
	Timeout
			cycles, or.983ms for a 33-MHz bus.
			• When 1, the value is 210 PCI clock cycles, or 30.7 ∝ s for a 33-MHz
			bus.
			• Reset value is 0
			Disables the primary master timeout counter.
	Primary		• When 0, the primary master timeout counter is enabled and uses the
			value specified by the Primary Master timeout bit.
	Master
4		R/W	• When 1, the primary master timeout counter is disabled. The 21555
	Timeout
			waits indefinitely for a primary bus initiator to repeat a delayed
	Disable
			transaction.
			• Reset value is 0
			Disables the secondary master timeout counter.
	Secondary		• When 0, the secondary master timeout counter is enabled and uses
			the value specified by the Secondary Master Timeout bit.
	Master
5		R/W	• When 1, the secondary master timeout counter is disabled. The 21555
	Timeout
			waits indefinitely for a secondary bus initiator to repeat a delayed
	Disable
			transaction.
			• Reset value is 0
			Controls how the 21555 initiates delayed transactions on the target bus.
			• When 0, the 21555 uses a round-robin arbitration scheme to
			determine which transaction is attempted. After receiving a target retry
			in response to a delayed transaction, the 21555 can initiate a different
	Delayed		queued delayed transaction.
6	Transaction	R/W	• When 1, When a target retry is received in response to a delayed
	Order Control		transaction, the 21555 continues to attempt that same transaction until
			a response other than target retry is received. The 21555 does not
			initiate other delayed transactions until the above condition is
			satisfied.
			• Reset value is 0.
			SERR# forward enable.
	SERR#		When 0, the 21555 does not assert p_serr_l as a result of s_serr_l
			assertion.
7	Forward	R/W
			When 1, the 21555 asserts p_serr_l when s_serr_l is detected asserted
	Enable
			and the primary SERR# Enable bit is set.
			Reset value is 0

21555 Non-Transparent PCI-to-PCI Bridge User Manual 157