I2O Support

The 21555 implements the following hardware for the Inbound Queue:

•Table 85, “I2O Inbound Queue” on page 166 register at CSR offset 40h.

•Table 87, “I2O Inbound Free_List Head Pointer” on page 167 at CSR offset 48h.

•Table 88, “I2O Inbound Post_List Tail Pointer” on page 167 at CSR offset 4Ch.

•Table 91, “I2O Inbound Post_List Counter” on page 168 at CSR offset 58h.

•Table 92, “I2O Inbound Free_List Counter” on page 168 at CSR offset 5Ch.

•Table 83, “I2O Inbound Post_List Status” on page 165 at CSR offset 38h.

•Table 84, “I2O Inbound Post_List Interrupt Mask” on page 166 at CSR offset 3Ch.

When the host processor has a message to pass to the local processor, it first reads the Inbound Queue location at 40h to remove an empty MFA from the Inbound Free_List. The 21555 maintains an on silicon 2 Dword buffer to hold the next two empty MFAs from the Inbound Free_List. When this buffer is not empty, the 21555 returns TRDY# and the next empty MFA from its buffer. When the internal buffer empties as a result of this read operation, and if the Inbound Free_List Counter is non-zero, the 21555 automatically reads one or two more MFAs from the Inbound Free_List as described in the following paragraph.

When the 2 Dword buffer is empty, the 21555 treats a read to location 44h as a delayed memory read transaction. The address that the 21555 uses to initiate the transaction on the secondary bus is the current value of the Outbound Post_List Head Pointer. When the Outbound Post_List Counter is non-zero, the 21555 places the read request in a downstream delayed transaction queue entry reserved for fetching outbound MFAs as follows:

•When the Outbound Post_List Counter is 2 or higher, the 21555 performs a 2 Dword secondary bus memory read starting at the location addressed by the Outbound Post_List head pointer and places the read data in the 2 Dword buffer.

•When the Outbound Post_List Counter is 1, the 21555 performs a single Dword read.

When the read completes on the secondary bus, the 21555 decrements the Outbound Post_List Counter by 1 or 2, respectively. The 21555 also increments the Outbound Post_List Head Pointer by either 1 or 2 Dwords, respectively. When the initiator repeats the read of CSR location 44h, the 21555 returns the next MFA to the host.

When the Inbound Free_List Counter is zero and the prefetch buffer is empty, the 21555 immediately returns FFFFFFFFh to the host and does not enter the transaction in the delayed transaction queue. The 21555 also does not decrement the Inbound Free_List Counter or increment the Inbound Free_List Head pointer.

Once the host obtains an empty MFA from the Inbound Free_List, it may then post a message to the local processor. The host processor posts a message to the Inbound Queue by writing the MFA to offset 40h. The 21555 treats the write to location 40h as a posted write; that is, it returns TRDY# to the initiator and places the write data in the posted write queue. The 21555 translates the address to the current value of the Inbound Post_List Tail Pointer. Once the MFA is queued in the posted write buffer, the 21555 increments the Inbound Post_List Tail Pointer by 1. The 21555 can continue to accept posted inbound MFAs as long as there is room in the downstream posted write queue. The 21555 performs a secondary bus memory write of this data to the location addressed by the Inbound Post_List Tail Pointer. When this write is completed on the secondary bus, the 21555 increments the Inbound Post_List counter by 1. As long as the Inbound Post_List counter is non-zero, the 21555 sets the Inbound Post_List status to 1, and asserts s_inta_l if the Inbound Post_List Mask bit is zero. Signal s_inta_l remains asserted until either the Inbound Post_List counter is zero or the Inbound Post_List Mask bit is set.

The local processor manages the removal of the MFA from the Inbound Post_List and the replacement of the empty MFA to the Inbound Free_List in software. The 21555 does not implement inbound queue pointers that would be used by the local processor. However, the local processor must manage the 21555’s Inbound Post_List counter when it removes an MFA. The Inbound Free_List Counter is needed so that the 21555 can determine when the Inbound Free_List is empty and must return FFFFFFFFh to the host processor instead of an empty MFA. When the local

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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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