Intel 21555 user manual 163

List of Registers

Table 79. Chip Status Register

All of the following conditions can cause the assertion of p_serr_l or s_serr_l if the corresponding SERR# enable bit is set and the disable bit for this condition is not set.

•Primary byte offset: D1:D0h

•Secondary byte offset: D1:D0h

Bit	Name	R/W	Description
	Downstream		This bit is set to a 1 and p_serr_l is conditionally asserted when the
			21555 discards a downstream posted write transaction after receiving
3	Posted Write	R/W1TC	224 target retries from the secondary bus target (Retry counters must
	Data		not be disabled).
	Discarded
			Reset value is 0
7:4	Reserved	R	Reserved. Returns 0 when read.
	Upstream		This bit is set to a 1 and s_serr_l is conditionally asserted when the
	Delayed
			secondary master timeout counter expires and an upstream delayed
8	Transaction	R/W1TC
			transaction completion is discarded from the 21555’s queues.
	Master
			Reset value is 0
	Time-out
	Upstream		This bit is set to a 1 and s_serr_l is conditionally asserted when the
	Delayed		21555 discards an upstream delayed read transaction request after
9	Read	R/W1TC	receiving 224 target retries from the primary bus target (Retry
	Transaction		counters must not be disabled).
	Discarded		Reset value is 0
	Upstream		This bit is set to a 1 and s_serr_l is conditionally asserted when the
	Delayed		21555 discards an upstream delayed write transaction request after
10	Write	R/W1TC	receiving 224 target retries from the primary bus target (Retry
	Transaction		counters must not be disabled).
	Discarded		Reset value is 0
	Upstream		This bit is set to a 1 and s_serr_l is conditionally asserted when the
			21555 discards an upstream posted write transaction after receiving
11	Posted Write	R/W1TC	224 target retries from the primary bus target (Retry counters must not
	Data		be disabled).
	Discarded
			Reset value is 0
15:12	Reserved	R	Reserved. Returns 0 when read.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 163