I2O Support

and asserts p_inta_l to indicate to the host processor that one or more MFAs exist in the Outbound Post_List . Signal p_inta_l remains asserted until either the Outbound Post_List Counter is zero and the

outbound prefetch buffer empties, or the Outbound Post_List Mask bit is set.

The host processor removes the message from the Outbound Post_List by reading the 21555 CSR offset 44h. The 21555 maintains a 2 Dword outbound prefetch buffer to hold the next two MFAs from the Outbound Post_List. When this buffer is not empty and the Outbound Post_List Counter is non-zero, the 21555 returns TRDY# and the next MFA from its buffer. When the internal buffer empties as a result of this read operation, the 21555 automatically reads one or two more MFAs from the Outbound Post_List as described in the following paragraph.

When the 2 Dword buffer is empty, the 21555 treats a read to location 44h as a delayed memory read transaction. The address that the 21555 uses to initiate the transaction on the secondary bus is the current value of the Outbound Post_List Head Pointer. When the Outbound Post_List Counter is non-zero, the 21555 places the read request in a downstream delayed transaction queue entry reserved for fetching outbound MFAs as follows:

•When the Outbound Post_List Counter is 2 or higher, the 21555 performs a 2 Dword secondary bus memory read starting at the location addressed by the Outbound Post_List head pointer and places the read data in the 2 Dword buffer.

•When the Outbound Post_List Counter is 1, the 21555 performs a single Dword read.

When the read completes on the secondary bus, the 21555 decrements the Outbound Post_List Counter by 1 or 2, respectively. The 21555 increments the Outbound Post_List Head Pointer by either 1 or 2 Dwords, respectively, as well. When the initiator repeats the read of CSR location 44h, the 21555 returns the next MFA to the host.

When the Outbound Post_List Counter is zero and the prefetch buffer is empty, the 21555 immediately returns FFFFFFFFh to the host and does not enter the transaction in the delayed transaction queue and also does not decrement the Outbound Post_List Counter. When the counter decrements to zero and the 2 Dword prefetch buffer is empty, the 21555 deasserts p_inta_l, indicating that there are no more posted MFAs in the Outbound Queue.

Once the host processor consumes the outbound message from the local processor, it replaces the empty MFA onto the end of the Outbound Free_List. When the host processor replaces the empty MFA to the Outbound Free_List, it writes the Outbound Queue at the 21555 CSR offset 44h. The 21555 treats the write to location 44h as a posted write; that is, it returns TRDY# to the initiator and places the write data in the downstream posted write queue. The 21555 translates the address to the current value of the Outbound Free_List tail pointer. Once the empty MFA is queued in the posted write buffer, the 21555 increments the Outbound Free_List tail pointer. The 21555 can continue to accept writes to this address as long as there is room in the downstream posted write queue. The 21555 writes the data to the secondary bus location addressed by the Outbound Free_List tail pointer. When the write is completed, the 21555 increments the Outbound Free_List counter.

14.3Notes

•Read transactions to I2O Inbound and Outbound Queues at 40h and 44h are not ordered with respect to transactions in the posted write or delayed transaction queues. Reads to these two registers will not flush posted writes. Write transactions to these registers are placed in the posted write queue, and follow the same ordering rules as other posted memory writes.

•When the 21555 detects parity errors, a master abort or target abort during a read or write access to the Inbound or Outbound Queues, the 21555 treats the error condition the same way as it does any other delayed read or posted write.

•The 21555 queue pointers support FIFO sizes of 256, 512, 1K, 2K, 4K, 8K, 16K, and 32K entries. The number of entries is selectable in the Table 78, “Chip Control 1 Register” on page 160. The wrap function for all of the I2O pointers maintained by the 21555 is performed in hardware; therefore, all FIFOs must be located in an aligned address boundary.

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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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