Intel 21555 user manual Chip Control 0 Register Sheet 3

List of Registers

Table 77. Chip Control 0 Register (Sheet 3 of 4)

This register may be preloaded by serial ROM or programmed by the local processor before host configuration.

•Primary byte offset: CD:CCh

•Secondary byte offset: CD:CCh

Bit	Name	R/W	Description
			Controls prefetching for upstream dual address transactions using the
			memory read bus command.
	Upstream		When 0, prefetching is performed for upstream DAC memory reads.
8	DAC Prefetch	R/W	When 1, upstream DACs using the memory read bus command are not
	Disable		prefetched; transactions are limited to a single Dword and byte enables
			are preserved.
			Reset value is 0
			Enables multiple devices to be attached to the ROM interface.
			• When 0, only the parallel and serial ROM can be attached to the ROM
	Multiple		interface. The PROM (PROM) chip select is driven on the pr_cs_l pin.
9		R/W	• When 1, multiple devices may be attached to the ROM interface. All
	Device Enable
			chip selects with the exception of the serial ROM are decoded from
			the upper address lines of the ROM interface.
			• Reset value is 0
			This bit prevents the primary bus from accessing configuration space. This
			allows the local processor to access the 21555 registers before the host
			processor accesses them.
			This bit can be written from the secondary interface only. The local
			processor must write this bit to a 0 to allow the 21555 to be configured by
	Primary		the host processor, unless preloaded to 0 by serial ROM.
10	Access	R/(WS)	• When 0, the 21555 configuration space can be accessed from both
	Lockout		interfaces.
			• When 1, the 21555 configuration space can only be accessed from
			the secondary interface. Primary bus accesses, with the exception of
			the Reset Control Register, receive a target retry.
			• Reset value is 1 when pr_ad[3] is high during reset, 0 when pr_ad[3]
			is low during reset.
			Secondary clock output disable. (refer to Table 20)
	Secondary		• When 0, signal s_clk_o is driven as a buffered copy of p_clk.
11		R/W	• When 1, signal s_clk_o is disabled and driven low.
	Clock Disable
			• Reset value is 0 when pr_ad[5] is high during primary bus reset; 1
			when pr_ad[5] is low during primary bus reset.

158 21555 Non-Transparent PCI-to-PCI Bridge User Manual