Chip Control 1 Register Sheet 1 | Intel 21555 manual

List of Registers

Table 78. Chip Control 1 Register (Sheet 1 of 3)

This register may be preloaded by serial ROM or programmed by the local processor before host configuration.

• Primary byte offset: CF:CEh

• Secondary byte offset: CF:CEh

Bit	Name	R/W	Description

			Controls the queue full threshold limit of the downstream posted write
			queue. When the queue is designated full, the 21555 returns retry to posted
			writes on the primary bus. Otherwise, the 21555 accepts write data into the
	Primary		posted write queue.
	Primary		• When 0, posted write queue full when less than a cache line is free to
0	Posted Write	R/W
	Threshold		post data.
			• When 1, posted write queue full when less than a half cache line (for
			CLS=8,16,32) is free to post data.
			• Reset value is 0b

			Controls the queue full threshold limit of the upstream posted write queue.
			When the queue is designated full, the 21555 returns retry to posted writes
			on the secondary bus. Otherwise, the 21555 accepts write data into the
	Secondary		posted write queue.
	Secondary		• When 0, posted write queue full when less than a cache line is free to
1	Posted Write	R/W
	Threshold		post data.
			• When 1, posted write queue full when less than a half cache line (for
			CLS=8,16,32) is free to post data.
			• Reset value is 0b

			Controls the read data queue threshold for initiating read transactions on
			the primary bus. When the amount of read data in the queue exceeds the
			threshold, the 21555 does not initiate a pending upstream delayed memory
			read transaction on the primary bus. The following values control when the
			21555 initiates a memory read:
			• 00b: At least 8 Dwords free in read data queue for all memory read
	Primary		commands
3:2	Delayed	R/W	• 01b: Illegal (uses the same behavior as 00b)
3:2	Read	R/W
	Read		• 10b: At least one cache line free for MRL and MRM, 8 Dwords free for
	Threshold
	Threshold		memory read
			memory read
			• 11b: At least one cache line free for all memory read commands
			NOTE: The secondary bus cache line size is used for the threshold
			calculation.
			Reset value is 00b

			Controls the read data queue threshold for initiating read transactions on
			the secondary bus. When the amount of read data in the queue exceeds
			the threshold, the 21555 does not initiate a pending downstream delayed
			memory read transaction on the secondary bus. The following values
			control when the 21555 initiates a memory read:
			• 00b: At least 8 Dwords free in read data queue for all memory read
	Secondary		commands
5:4	Delayed	R/W	• 01b: Illegal (uses the same behavior as 00b)
5:4	Read	R/W
	Read		• 10b: At least one cache line free for MRL and MRM, 8 Dwords free for
	Threshold
	Threshold		memory read
			memory read
			• 11b: At least one cache line free for all memory read commands
			NOTE: The primary bus cache line size is used for the threshold
			calculation.
			Reset value is 00b

160	21555 Non-Transparent PCI-to-PCI Bridge User Manual

21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.

Intel 21555 user manual Chip Control 1 Register Sheet 1

Models: 21555

Table 78. Chip Control 1 Register (Sheet 1 of 3)

Bit

21555 specifications