Intel 21555 user manual Downstream and Upstream Configuration Address Registers, Cfgaddr

List of Registers

Table 46. Downstream and Upstream Configuration Address Registers

This section describes both the downstream and upstream versions of the registers. These registers are also mapped in memory and I/O space.

Offsets	Downstream Configuration Address	Upstream Configuration Address
Primary byte	83:80h	8B:88h (Reserved)
Secondary byte	83:80h (Reserved)	8B:88h
CSR Space	003:000h	00B:008h

Bit	Name	R/W	Description
			This register contains the address for a configuration transaction to be
			generated on the target bus. The address is driven exactly as written in this
			register. This register should be written before the corresponding
		DCA:	Downstream or Upstream Configuration Data register is accessed. Once
			the Downstream or Upstream Configuration Data register is accessed, the
	CFG_ADDR	R/(WP)	transaction is initiated on the secondary or primary bus, respectively. When
31:0			the semaphore method is used, a master should not write to this register
	(CA)		unless the master has successfully read a 0 from the Downstream or
		UCA:
			Upstream Configuration Own bit.
		R/(WS)	The Downstream Configuration Address register cannot be written from the
			secondary interface.
			The Upstream Configuration Address register cannot be written from the
			primary interface.

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