Serial ROM Interface

Prior to a SROM write or write all transaction, the 8-bit write data must be written in the ROM Data CSR.

To initiate the SROM access, the SROM Start bit in the ROM Control CSR is written with a 1 (the PROM Start bit must be written to a 0 with this access). The 21555 then initiates the SROM access. When the SROM access is complete, the 21555 automatically clears the SROM Start bit. When the operation is a read, the data then can be read from the ROM Data register.

The write, write all, erase, and erase all commands may take 10 ms or more to complete, internal to the ROM. A poll of the SROM must be performed to discover whether these operations are complete. For these commands, when the SROM access is initiated, the 21555 also sets the SROM_POLL bit in the Table 112, “ROM Control Register” on page 178. This bit remains asserted after the 21555’s access to the SROM completes. The SROM must be polled by CSR access and return a ready indication to clear the SROM_POLL bit.

The SROM is polled by the 21555 when the SROM Start bit is written with a 1 when the SROM_POLL bit is set. The 21555 asserts sr_cs and drives sr_di (pin pr_ad[1]) low. When the SROM drives sr_do (pin pr_ad[2]) high in response, it has completed the operation internally and the 21555 clears the SROM_POLL bit. The SROM is now ready for another access.

Note: The SROM_POLL bit must be set for the 21555 to poll the SROM, otherwise the 21555 initiates another SROM access if the SROM Start bit is written.

A summary of the actions needed for a SROM read access follows:

1.The initiator writes the byte address and the opcode in the ROM Address CSR.

2.The initiator writes the SROM Start bit to a 1 and the PROM Start bit to a 0 in the ROM Control CSR.

3.When the SROM Start bit in the ROM Control CSR is read as a zero, the initiator may read the 8-bit data from the ROM Data register.

A summary of the actions needed for a write operation follows:

1.The initiator writes the byte address and the opcode in the ROM Address CSR.

2.The initiator writes the 8-bit data in the ROM Data CSR.

3.The initiator writes the SROM Start bit to a 1 and the PROM Start bit to a 0 in the ROM Control CSR in the same CSR access.

4.When the SROM Start bit in the ROM Control CSR is read as a zero, the initiator polls the SROM to test for write completion by writing the SROM Start bit to a 1.

5.When the SROM Start bit in the ROM Control CSR is read as a zero, the SROM_POLL bit indicates the status of the polling operation. When SROM_POLL is read as a one, the SROM should be polled again. When SROM_POLL is read as a 0, the operation is complete.

The erase, erase all, write enable, and write disable all use write protocol. For all of these operations, however, the ROM Data register does not need to be written. In addition, the write enable and write disable operations do not require polling for completion. Figure 19 through Figure 24 show the timing diagrams for SROM read, write, write all, write enable, write disable, erase, erase all, and check status (polling) operations.

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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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