PCI Bus Transactions

5.2.1Memory Write Transactions

As a target, the 21555 disconnects memory write transactions at the following address boundaries:

•An aligned 4KB address boundary.

•An aligned page address boundary for upstream transactions falling in the Upstream Memory 2 address range.

•An aligned cache line boundary, when the MW disconnect bit is set in configuration space.

When the posted write queue fills before the master terminates the transaction, the 21555 returns a target disconnect when the last queue entry is filled. The 21555 does not disconnect on an aligned address boundary, other than those noted in the previous paragraph, when the write queue is almost full. That is, the memory write queue full disconnect condition is optimized for burst length and not alignment.

As an initiator, when the 21555 has posted write data to deliver and the conditions listed in Section 5.2.2 for initiating an MWI transaction are not met, the 21555 uses the memory write command to deliver posted memory write data. The 21555 terminates the memory write burst when the last piece of data in the transaction is delivered, or if the transaction is in flow-through mode, when a queue empty condition is detected. In the latter case, the 21555 master terminates the transaction on the target bus, and then initiates a new transaction when a cache line amount of data is accumulated.

5.2.2Memory Write and Invalidate Transactions

As a target, the 21555 disconnects MWI transactions at the following address boundaries:

•An aligned 4 KB address boundary.

•An aligned page address boundary, for upstream transactions falling in the Upstream Memory 2 address range.

•An aligned cache line boundary, for MWI transactions when less than a cache line of available space remains in the posted write queue.

The 21555 disconnects an MWI on a cache line boundary when less than a cache line remains free in the posted write buffer. This is a different queue full disconnect behavior than that used for the memory write command. In this case, alignment is preserved at the expense of maximizing burst length.

When a master initiates an MWI transaction, it guarantees that it will supply one full cache line of data, or some multiple thereof. The 21555 initiates an MWI transaction on the target bus, regardless of whether the bus command was a memory write or an MWI on the initiator bus, when all of the following conditions are met:

•The MWI Enable bit is set in the Command register corresponding to the target interface.

•The target bus Cache Line Size is set to a valid value (8, 16, or 32 Dwords).

•At least one aligned cache line of data has been posted.

•All byte enables for the posted cache line are turned on.

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Intel 21555 user manual Memory Write Transactions, Memory Write and Invalidate Transactions
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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