Intel 21555 user manual Arbiter Control, Error Registers

List of Registers

16.11Arbiter Control

This chapter describes the arbitration control registers. See Chapter 10 for theory of operation information.

Table 115. Arbiter Control Register

This register may be preloaded by serial ROM or programmed by local processor before host configuration.

•Primary byte offset: D3:D2h

•Secondary byte offset: D3:D2h

Bit	Name	R/W	Description
			Each bit controls whether a secondary bus master is assigned to the high
			priority arbiter ring or the low priority arbiter ring. Bits [8:0] correspond to
			request inputs s_req_l[8:0], respectively. Bit [9] corresponds to the internal
9:0	Arbiter Control	R/W	21555 secondary bus request.
			• When 0, indicates that the master belongs to the low priority group.
			• When 1, indicates that the master belongs to the high priority group.
			• Reset value is 10 0000 0000b.
			Controls whether the 21555 parks on itself or on the last master to use the
			bus.
			• When 0, during bus idle, the 21555 parks the bus on the last master to
10	Bus Parking	R/W	use the bus.
	Control		• When 1, during bus idle, the 21555 parks the bus on itself. The bus
			grant is removed from the last master and internally asserted to the
			21555.
			• Reset value is 0b.
15:11	Reserved	R	Reserved. Returns 0 when read.

16.12Error Registers

This section describes the primary and secondary SERR# disable registers. See Chapter 12 for theory of operation information.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 183