Intel 21555 Control and Status Registers, Configuration Space Address Register Sheet 5, Byte

List of Registers

Table 32. Configuration Space Address Register (Sheet 5 of 5)

Byte		Reset Value		Write	Read
Offset	Register Name		Preload
		(Hex)		Access	Access
(Hex)
EC	CompactPCI Hot-Swap	06	—	Secondary	N
	Capability Identifier and Next
	Pointer Register, page 189
ED	Hot-Swap Cap ID	00	—	N	N
	Hot-Swap Next Ptr
	CompactPCI Hot-Swap Control
EE	Register, page 189	00x1000b	—	Y	N
	Hot-Swap Control
FF:F0	Reserved	00000000	—	N	Y

16.3Control and Status Registers

The control and status registers are memory mapped in the Primary CSR and Memory 0 Base Address window and the Secondary CSR Base Address window. These registers are I/O mapped in the Primary CSR I/O BAse Address window and the Secondary CSR I/O Base Address window. Offsets are referenced from these base addresses.

Table 33 lists the CSR summary. 017:014

Table 33. CSR Address Map (Sheet 1 of 5)

Byte
Offset	Register Name	Reset Value	Write Access	Read Access
(Hex)
	Downstream and Upstream Configuration
003:000	Address Registers, page 141	Indeterminate	Primary	Y
	Downstream Configuration Address
	Downstream Configuration Data and
007:004	Upstream Configuration Data Registers,	Indeterminate	Primary	Primary
	page 142
	Downstream Configuration Data
	Downstream and Upstream Configuration
00B:008	Address Registers, page 141	Indeterminate	Secondary	Y
	Upstream Configuration Address
	Downstream Configuration Data and
00F:00C	Upstream Configuration Data Registers,	Indeterminate	Secondary	Secondary
	page 142
	Upstream Configuration Data
010	Configuration Own Bits Register, page 142	00	N	Primary Read-
				0-to-set
	Configuration Own Byte 0
				Secondary
011	Configuration Own Byte 1	00	N
				Read-0-to-set
013:012	Configuration CSR, page 143	0000	Y	Y
	Configuration CSR
	Downstream I/O Address and Upstream I/O
017:014	Address Registers, page 144	Indeterminate	Primary	Y
	Downstream I/O Address

126 21555 Non-Transparent PCI-to-PCI Bridge User Manual