PCI Bus Transactions

When the initiator repeats the transaction using the same address, bus command, write data, and byte enables, then the 21555 returns the appropriate target termination when ordering rules allow. Otherwise, the 21555 continues to return target retry. The target terminations are listed in Table 13.

Table 13. Delayed Write Transaction Target Termination Returns

Target Bus Response

Initiator Bus Response

 

 

TRDY#

TRDY# and STOP# when multiple data phases are requested.

 

 

Target abort

Target abort

•TRDY# when Master Abort Mode bit = 0

Master abort

•Target abort when Master Abort Mode bit = 1

When the 21555 has a delayed completion to return to an initiator, and the initiator does not repeat the transaction before the Master Time-Out Counter for that interface expires, it discards the delayed completion transaction. When enabled to do so, the 21555 asserts SERR# on the initiator bus. The Master Time-Out Counter expiration value is either 210 or 215 PCI clock cycles, programmable in the Chip Control 0 configuration register. The Master Time-Out Counter is disabled when the Master Time-Out Disable bit in the Chip Control 0 configuration register is zero.

5.4Delayed Read Transactions

This section discusses the these Delayed Read Transactions:

•Section 5.4.1, “Nonprefetchable Reads” on page 56.

•Section 5.4.2, “Prefetchable Reads” on page 57.

•Section 5.4.3, “Prefetchable Read Transactions Using the 64-bit Extension” on page 57.

•Section 5.4.4, “Read Performance Features and Tuning Options” on page 57.

The 21555 uses delayed transactions when forwarding any type of read from one PCI interface to the other. Read types are I/O, memory, memory read line, and memory read multiple.

Delayed transactions are also used for parallel ROM reads and CSR or configuration register reads that cause the

21555 to initiate a PCI read transaction, such as:

•CSR or configuration register read access that causes the 21555 to initiate a configuration read transaction.

•CSR read access that causes the 21555 to initiate an I/O read transaction.

The delayed read transaction protocol is similar to that of delayed write transactions, with the exception that 64-bit transfers may be used for delayed-memory read transactions. When an I/O or memory read intended for the other PCI bus is first initiated, the 21555 returns a target retry. The 21555 queues the transaction information if the delayed transaction queue is not full and a transaction having the same address and bus command does not already exist in the delayed transaction queue. This includes address, bus command, byte enables for nonprefetchable reads.

Note: The byte enables are not checked when the 21555 decides whether to queue a delayed write transaction.

When the transaction queued is a result of a CSR or configuration register read, the 21555 queues the appropriate data based on the type of access desired, the address contained in the register, and the byte enables used for the data register access. This phase of the delayed transaction is called a Delayed Read Request (DRR).

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Intel 21555 user manual Delayed Read Transactions, Delayed Write Transaction Target Termination Returns
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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