Intel 21555 user manual Initiation of Configuration Transactions by

Address Decoding

Accesses to the 21555 configuration space are not ordered with respect to transactions in the 21555 queues. That is, the 21555 responds immediately to configuration transactions regardless of what transactions exist in the upstream and downstream queues. Exceptions to this are configuration accesses that result in the initiation of configuration and I/O transactions by the 21555. These transactions are entered in the delayed transaction queue and ordered appropriately with respect to other delayed transactions and posted writes in the 21555 queues.

4.5.2Initiation of Configuration Transactions by 21555

Usually, the host processor configures primary bus devices and the local processor configures secondary bus devices, so forwarding of configuration transactions is not typically necessary. However, to support other configuration methods, the 21555 implements a mechanism that enables initiation of Type 0 or Type 1 configuration accesses on either the primary bus or the secondary bus. This mechanism is different from the hierarchical mechanisms supported by PPBs. Instead, two pairs of device-specific registers contain the address and data that are used to initiate the configuration transaction. One pair is used to generate transactions on the primary interface; the other is used to generate transactions on the secondary interface:

•The Upstream Configuration Address and Upstream Configuration Data registers contain the address and data of the configuration transaction to be initiated on the primary bus.

•the Downstream Configuration Address and Downstream Configuration Data registers contain the address and data of the configuration transaction to be initiated on the secondary bus.

In addition, the Configuration CSR and Configuration Own Bits register are used for configuration transaction generation. All of these registers are mapped into both device specific configuration space and the 21555 CSR space. The upstream address and data registers can be written from the secondary interface only, and the downstream address and data registers can be written from the primary interface only. Downstream and upstream configuration address registers can be read from either interface. Otherwise, these registers respond as reserved.

To generate a configuration transaction, the corresponding Upstream or Downstream Configuration Control bit in the Configuration CSR must be set. Otherwise, the corresponding Configuration Data registers are treated as reserved registers. The Configuration Data registers are also treated as reserved registers in memory space.

The Upstream or Downstream Configuration Address register must be written with the address to be driven before the corresponding data register is accessed. This address is driven on the AD lines exactly as written in the register. Therefore, a Type 0 format must be used to generate a

Type 0 configuration transaction, and a Type 1 format must be used to generate a Type 1 configuration transaction. The upper 21 bits of a Type 0 address format are used as IDSEL signals and are specific to the motherboard or add-in card application.

The configuration transaction is initiated by the 21555 when the Upstream or Downstream Configuration Data register is either read or written from the secondary or primary interface, respectively. These registers must be accessed by either a configuration transaction or an I/O transaction to initiate the transaction. The 21555 uses the same byte enables that the initiator used to read or write the register. The 21555 responds to the access of the Upstream or Downstream Configuration Data register with a target retry until the access is completed on the target bus. When the access is completed, the 21555 returns the corresponding target termination and, if a read, the read data on a subsequent attempt of the transaction by the initiator. When the Delayed Transaction Target Retry Counter expires, that is, 224 target retries are received from the target, the 21555 returns a target abort to the initiator. The Delayed Transaction Target Retry Counter may be disabled, and thus does not limit the number of retries, by setting the Retry Counter Disable bit in the Chip Control 0 configuration register.

The 21555 can be enabled to respond to configuration transactions that it generates by setting the appropriate Downstream/Upstream Self-Response Enable bit in the Configuration CSR. For the 21555 to respond, the transaction must assert the 21555’s IDSEL signal on that interface, and it must be a Type 0 configuration transaction. When this bit is not set, the 21555 will not respond to any configuration transactions that it generates, and these transactions may end in master abort.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 45