Intel 21555 user manual PPB Feature Comparison

Introduction

Table 3 shows compares a 21555 and to a transparent PPB.

Table 3. 21555 and PPB Feature Comparison

Feature	Non-Transparent PPB or 21555	Transparent PPB
	• Adheres to PPB ordering rules.
	• Uses posted writes and delayed	• Adheres to PPB ordering rules.
Transaction	transactions.	• Uses posted writes and delayed
		transactions.
forwarding	• Adheres to PPB transaction error
	and parity error guidelines,	• Adheres to PPB transaction error and
	although some errors may be	parity error guidelines.
	reported differently.
	• Base address registers (BARs)
	are used to define independent	• PPB base and limit address registers are
	downstream and upstream	used to define downstream forwarding
Address decoding	forwarding windows.	windows.
	• Inverse decoding is only used for	• Inverse decoding for upstream
	upstream transactions above the	forwarding.
	4GB boundary.
Address	Supported for both memory and I/O	None. Flat address model is assumed.
translation	transactions.
	• Downstream devices are not
	visible to host.	• Downstream devices are visible to host.
	• Does not require hierarchical
		• Requires hierarchical configuration code
	configuration code (Type 0
		(Type 1 configuration header).
	configuration header).
Configuration	• Does not respond to Type 1	• Forwards and converts Type 1
		configuration transactions.
	configuration transactions.
	• Supports configuration access	• Does not support configuration access
		from the secondary bus. Same set of
	from the secondary bus.
		configuration registers is used to control
	• Implements separate set of
		both primary and secondary interfaces.
	configuration registers for the
	secondary interface.
	Includes features such as doorbell
Run-time resources	interrupts, I20 message unit, and so	Typically has only configuration registers; no
	on, that must be managed by the	device driver is required.
	device driver.
	Generates secondary bus clock
Clocks	output.	Generates one or more secondary bus clock
	Asynchronous secondary clock input	outputs.
	is also supported.
	Implements secondary bus arbiter.
Secondary bus	This function can be disabled.	Implements secondary bus arbiter.
	Drives secondary bus AD, C/BE#,	Drives secondary bus AD, C/BE#, and PAR
central functions
	and PAR during reset. This function	during reset.
	can be disabled.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 17