Intel 21555 user manual Primary Interface Configuration Space Address Map, Vendor ID Register

List of Registers

Table 57. Primary Interface Configuration Space Address Map

Byte 3	Byte 2	Byte 1	Byte 0	Primary	Secondary
				Offset	Offset
Device ID1		Vendor ID1		00h	40h
Primary Status		Primary Command		04h	44h
Primary Class Code2			Revision ID1	08h	48h
BIST1,2	Header Type1	Primary MLT	Primary CLS	0Ch	4Ch
Subsystem ID1,2		Subsystem Vendor ID1,2		2Ch	6Ch
Reserved			Cap_Ptr1	34h	74h
Primary	Primary	Primary Interrupt	Primary Interrupt	3Ch	7Ch
Max_Lat2	Min_Gnt2	Pin	Line

1.Primary and secondary configuration registers are shared.

2.Register or a portion of the register may be preloaded using the serial ROM interface.

Table 58. Secondary Interface Configuration Space Address Map

Byte 3	Byte 2	Byte 1	Byte 0	Primary	Secondary
				Offset	Offset
Device ID1		Vendor ID1		40h	00h
Secondary Status		Secondary Command		44h	04h
Secondary Class Code1			Revision ID1	48h	08h
BIST1,2	Header Type1	Secondary MLT	Secondary CLS	4Ch	0Ch
Subsystem ID1,2		Subsystem Vendor ID1,2		6Ch	2Ch
Reserved			Cap_Ptr1	74h	34h
Secondary	Secondary	Secondary	Secondary	7Ch	3Ch
Max_Lat2	Min_Gnt2	Interrupt Pin	Interrupt Line

1.Primary and secondary configuration registers are shared.

2.Register or a portion of the register may be preloaded using the serial ROM interface.

Table 59. Vendor ID Register

• Primary byte offset: 01:00h and 41:40h

• Secondary byte offset: 41:40h and 01:00h

Bit	Name	R/W	Description
15:0	Vendor ID	R	The Vendor ID identifies Intel® as the vendor of this device and is internally
			hardwired to be 8086 hex.

Table 60. Device ID Register

• Primary byte offset: 03:02h and 43:42h

• Secondary byte offset: 43:42h and 03:02h

Bit	Name	R/W	Description
15:0	Device ID	R	Device ID identifies this device as the 21555 and is internally hardwired to be
			B555h.

148 21555 Non-Transparent PCI-to-PCI Bridge User Manual