Intel 21555 Primary PCI Bus Interface Signals Sheet 1, Signal Name Type Description

Signal Descriptions

3.1Primary PCI Bus Interface Signals

Table 6 describes the primary PCI bus interface signals. The letters in the “Type” column are described in Table 1.

Table 6. Primary PCI Bus Interface Signals (Sheet 1 of 2)

Signal Name	Type	Description
		Primary PCI interface address and data. These signals are a 32-bit multiplexed
		address and data bus. During the address phase or phases of a transaction, the
p_ad[31:0]	TS	initiator drives a physical address on p_ad[31:0].
		During the data phases of a transaction, the initiator drives write data, or the target
		drives read data, on p_ad[31:0]. When the primary PCI bus is idle, the 21555 drives
		p_ad to a valid logic level when p_gnt_l is asserted.
		Primary PCI interface command and byte enables. These signals are a multiplexed
		command field and byte enable field. During the address phase or phases of a
		transaction, the initiator drives the transaction type on p_cbe_l[3:0].
p_cbe_l[3:0]	TS	When there are two address phases, the first address phase carries the
		dual-address command and the second address phase carries the transaction type.
		For both read and write transactions, the initiator drives byte enables on
		p_cbe_l[3:0] during the data phases. When the primary PCI bus is idle, the 21555
		drives p_cbe_l to a valid logic level when p_gnt_l is asserted.
		Primary PCI interface DEVSEL#. Signal p_devsel_l is asserted by the target,
		indicating that the device is responding to the transaction. As a target, the 21555
		decodes the address of a transaction initiated on the primary bus to determine
		whether to assert p_devsel_l.
p_devsel_l	STS	As an initiator of a transaction on the primary bus, the 21555 looks for the assertion
		of p_devsel_l within five clock cycles of p_frame_l assertion; otherwise, the 21555
		terminates the transaction with a master abort.
		Upon completion of a transaction, p_devsel_l is driven to a deasserted state for one
		clock cycle and is then sustained by an external pull-up resistor.
		Primary PCI interface FRAME#. Signal p_frame_l is driven by the initiator of a
		transaction to indicate the beginning and duration of an access on the primary PCI
		bus. Signal p_frame_l assertion (falling edge) indicates the beginning of a PCI
p_frame_l	STS	transaction. While p_frame_l remains asserted, data transfers can continue. The
		deassertion of p_frame_l indicates the final data phase requested by the initiator.
		Upon completion of a transaction, p_frame_l is driven to a deasserted state for one
		clock cycle and is then sustained by an external pull-up resistor.
		Primary PCI interface IDSEL. Signal p_idsel is used as the chip select line for Type
p_idsel	I	0 configuration accesses to 21555 configuration space from the primary bus. When
		p_idsel is asserted during the address phase of a Type 0 configuration transaction,
		the 21555 responds to the transaction by asserting p_devsel_l.
		Primary PCI interface IRDY#. Signal p_irdy_l is driven by the initiator of a
		transaction to indicate the initiator’s ability to complete the current data phase on the
		primary PCI bus.
		During a write transaction, assertion of p_irdy_l indicates that valid write data is
p_irdy_l	STS	being driven on the p_ad bus.
		During a read transaction, assertion of p_irdy_l indicates that the initiator is able to
		accept read data for the current data phase. Once asserted during a given data
		phase, p_irdy_l is not deasserted until the data phase completes.
		Upon completion of a transaction, p_irdy_l is driven to a deasserted state for one
		clock cycle and is then sustained by an external pull-up resistor.

24 21555 Non-Transparent PCI-to-PCI Bridge User Manual