Intel 21555 user manual Primary and Secondary Interrupt Pin Registers

List of Registers

Table 73. Primary and Secondary Interrupt Pin Registers

	Offsets			Primary Interrupt Pin	Secondary Interrupt Pin
	Primary byte			3Dh	7Dh
	Secondary byte			7Dh	3Dh
	Bit	Name	R/W	Description
				This register indicates which PCI interrupt pin the 21555 uses on the
7:0		Interrupt Pin	R	corresponding bus. This is a read-only register and always returns 1 when
				read indicating that the 21555 uses INTA#.

Table 74. Primary and Secondary Minimum Grant Registers

These registers may be preloaded through the serial ROM. The Primary Minimum Grant register may also be programmed by the local processor.

	Offsets			Primary Minimum Grant		Secondary Minimum Grant
	Primary byte			3Eh		7Eh
	Secondary byte			7Eh		3Eh
	Bit	Name	R/W		Description
			PMG: R/(WS)		Specifies how long of a burst period the 21555 needs on the
7:0		MIN_GNT (MG)			corresponding bus in units of 1/4 ∝ sec. Reads as 0 before
			SMG: R
					preload.

Table 75. Primary and Secondary Maximum Latency Registers

These registers may be preloaded through the serial ROM. The Primary Maximum Latency register may also be programmed by the local processor.

	Offsets			Primary Maximum Latency		Secondary Maximum Latency
	Primary byte			3Fh		7Fh
	Secondary byte			7Fh		3Fh
	Bit	Name	R/W		Description
7:0		MAX_LAT	PML: R/(WS)		Specifies how often the 21555 needs to gain access to the
		(ML)	SML: R		corresponding bus in units of 1/4 ∝ sec. Reads as 0 before preload.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 155