I2O Support

processor removes the message from the Inbound Post_List, it must write bit 31 of the Inbound

Post_List counter with a 0, which causes the 21555 to decrement the Inbound Post_List counter by 1. When the counter decrements to zero, the 21555 deasserts s_inta_l, indicating that there are no more posted MFAs in the Inbound Queue.

Once the local processor consumes the inbound message from the host, it replaces the empty MFA onto the end of the Inbound Free_List. Again, the 21555 does not manage the pointers for this operation, so the local processor must manage this in software. However, the local processor manages the 21555’s Inbound Free_List Counter when it replaces an empty MFA. When the local processor replaces the empty MFA to the Inbound Free_List, it must write bit 31 of the Inbound Free_List Counter with a zero, which causes the 21555 to increment the

Inbound Free_List Counter by 1.

14.2Outbound Message Passing

An outbound message is passed from the local processor to the host processor in the following steps:

1.The local processor removes an empty MFA, if available, from the head of the Outbound Free_List.

2.The local processor posts an MFA containing the address of the message frame to the tail of the Outbound Post_List.

3.The I2O Controller interrupts the host processor, indicating that an MFA exists in the Outbound Post_List.

4.The host processor retrieves the MFA from the head of the Outbound Post_List.

5.After the host processor consumes the message, it replaces the empty MFA onto the tail of the Outbound Free_List.

The 21555 implements the following hardware for the Outbound Queue:

•Table 86, “I2O Outbound Queue” on page 166 register at CSR offset 44h.

•Table 89, “I2O Outbound Free_List Tail Pointer” on page 167 at CSR offset 50h.

•Table 90, “I2O Outbound Post_List Head Pointer” on page 167 at CSR offset 54h.

•Table 93, “I2O Outbound Post_List Counter” on page 169 at CSR offset 60h.

•Table 94, “I2O Outbound Free_List Counter” on page 169 at CSR offset 64h.

•Table 81, “I2O Outbound Post_List Status” on page 165at CSR offset 30h.

•Table 82, “I2O Outbound Post_List Interrupt Mask” on page 165 at CSR offset 34h.

When the local processor has a message to pass to the host processor, it must remove an empty MFA from the head of the Outbound Free_List. The 21555 does not implement outbound queue pointers that are used by the local processor. However, the local processor manages the 21555’s Outbound Free_List counter when it removes an empty MFA. When the local processor removes the empty MFA from the Outbound Free_List, it must write bit 31of the Outbound Free_List counter to a zero, causing the 21555 to decrement the Outbound Free_List counter by

1.The 21555 does not use the value of this counter internally, but makes this function available to track the number of empty MFAs in the Outbound Free_List

When the local processor posts a message to the Outbound Post_List, it must write bit 31 of the Outbound Post_List Counter to a zero, which causes the 21555 to increment the counter by 1. A non-zero value in the Outbound Post_List Counter indicates that the Outbound Post_List contains MFAs intended for the host processor. When the Outbound Post_List Mask bit is zero, upon detection of a non-zero value in the Outbound Post_List counter or if the onchip outbound prefetch buffer is not empty, the 21555 sets the Outbound Post_List status to 1

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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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