Intel 21555 Prefetchable Reads, Prefetchable Read Transactions Using the 64-bit Extension

PCI Bus Transactions

5.4.2Prefetchable Reads

The following transactions are considered by the 21555 to be prefetchable read transactions:

•Transactions using the memory read line command.

•Transactions using the memory read multiple command.

•Transactions using the memory read command that address a range configured as prefetchable.

During a prefetchable read, the 21555 speculatively reads data from the target before the initiator explicitly requests it. The amount of data read depends on the read command, the cache line size corresponding to the initiator bus, and whether the 21555 is in flow-through mode, as described in Table 15. The 21555 drives the byte enables to 0h for all data phases, regardless of the byte enables driven by the initiator of the transaction.

When the 21555 returns prefetchable read data to the initiator, it continues to return read data until the master deasserts FRAME# and IRDY# ending the transaction, or until the 21555 runs out of read data and the target disconnect is returned. When the master terminates the transaction, the 21555 discards the unconsumed read prefetch data. Read data is discarded at a rate of 8 Dwords per clock cycle. During read data discard, the 21555 is unable to return any other delayed transaction completions on the initiator bus or enqueue new delayed requests.

5.4.3Prefetchable Read Transactions Using the 64-bit Extension

The 21555 uses the 64-bit extension signals when implemented, to initiate and complete prefetchable read transactions.

As a target, the 21555 asserts ACK64# in response to the initiator’s assertion of REQ64# for prefetchable memory read transactions where the 21555 has more than 1 Dword of data to return. The 21555 returns 64 bits of data per data phase without inserting target wait states, with the exception of a temporary queue-empty condition during flow-through. When the 21555 has an odd number of Dwords to return to the initiator, it disconnects before delivering the last Dword. The last Dword is discarded.

As an initiator, the 21555 asserts REQ64# for all prefetchable memory reads that have a starting address on an aligned Quadword boundary (that is, address bit AD[2] = 0). This prevents the 21555 from accidentally prefetching over an aligned prefetch address boundary. The 21555 then accepts 64 bits of read data per data phase without inserting master wait states.

5.4.4Read Performance Features and Tuning Options

The 21555 implements several features and options that affect read performance when forwarding prefetchable read transactions.

5.4.4.1Read Flow-Through

When the bandwidth of the initiator PCI interface is less than or equal to the bandwidth of the target PCI interface, the 21555 may use flow-through, or streaming, operation when returning read data. When the initiator of a delayed prefetchable read transaction repeats the transaction, and the 21555 starts delivering read data on the initiator bus while it is still accepting data for that transaction on the target bus, the 21555 enters read flow-through mode. When in flow-through mode, the 21555 can sustain long read bursts up to a 4KB aligned address boundary, or up to a page address boundary for upstream transactions falling into Memory Range 2. The 21555 always stops the prefetching of reads at 4KB address boundaries. When the read data queue empties while the 21555 is in flow-through mode, the 21555 waits up to seven cycles and then disconnects if read data is still not available.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 57