Intel 21555 user manual Configuration Own Bits Register, Cfgdata

List of Registers

Table 47. Downstream Configuration Data and Upstream Configuration Data Registers

These registers are also mapped in memory and I/O space. This register is treated as a reserved register for all memory accesses.

Offsets	Downstream Configuration Data	Upstream Configuration Data
Primary byte	87:84h	8F:8Ch (Reserved)
Secondary byte	87:84h (Reserved)	8F:8Ch
CSR Space	007:004h	00F:00Ch

Bit	Name	R/W	Description
			This register contains the write data driven or the read data returned from a
			configuration transaction initiated by the 21555. The Downstream or
			Upstream Configuration Address register contains the address for this
			transaction, depending on the direction of the transaction.
			The transaction is initiated when this register is written (for a configuration
			write) or read (for a configuration read) and the corresponding
		DCD:	Configuration Control bit is a one.
			The byte enables used for this register access are the same byte enables
		R/(WP)
	CFG_DATA		used for the transaction driven on the target bus. A target retry is returned to
31:0			the initiator until the transaction has been completed on the target bus.
	(CD)
		UCD:	When the semaphore method is used, a master should not write to this
			register unless the master has successfully read a 0 from the Downstream
		R/(WS)
			or Upstream Configuration Own bit.
			The Downstream Configuration Data register is reserved when accessed
			from the secondary interface, or on either interface when the Downstream
			Configuration Enable bit is not set.
			The Upstream Configuration Data register is reserved when accessed from
			the primary interface, or on either interface when the Upstream
			Configuration Enable bit is not set.

Table 48. Configuration Own Bits Register

This register is also mapped in memory and I/O space.

• Primary byte offset: 91:90h

• Secondary byte offset: 91:90h

• CSR byte offset 011:010h.

Bit	Name	R/W	Description
			Indicates ownership of the Downstream Configuration Address and
			Downstream Configuration Data registers.
			• When 0, downstream Configuration Address and Downstream
			Configuration Data registers are not owned. When read as a 0
			from the primary interface, this bit is subsequently set to a 1 by
	Downstream	R0TS (P)	the 21555 when the Downstream Configuration Control bit is a 1.
0	Configuration		• When 1, a master owns Downstream Configuration Address and
		R(S)
	Own Bit		Downstream Configuration Data registers. When this semaphore
			method is used, other masters should not attempt to access
			these registers when this bit is a 1. This bit is automatically
			cleared once the configuration transaction has completed on the
			initiator bus.
			• Reset value is 0.

142 21555 Non-Transparent PCI-to-PCI Bridge User Manual